參數(shù)資料
型號(hào): MAX19708ETM+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 37/37頁(yè)
文件大小: 0K
描述: IC ANLG FRNT END 48-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 10
通道數(shù): 4
功率(瓦特): 36.9mW
電壓 - 電源,模擬: 3V
電壓 - 電源,數(shù)字: 3V
封裝/外殼: 48-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 48-TQFN-EP(7x7)
包裝: 帶卷 (TR)
MAX19708
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
_______________________________________________________________________________________
9
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL
≈ 10pF on all digital outputs, fCLK = 11MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN =
CCOM = 0.33F, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Maximum REFP/REFN/COM
Sink Current
ISINK
2mA
Differential Reference Output
VREF
VREFP - VREFN
+0.460
+0.512
+0.548
V
Differential Reference Temperature
Coefficient
REFTC
±18
ppm/°C
BUFFERED EXTERNAL REFERENCE (external VREFIN = 1.024V applied; VREFP, VREFN, VCOM levels are generated internally)
Reference Input Voltage
VREFIN
1.024
V
Differential Reference Output
VDIFF
VREFP - VREFN
0.512
V
Common-Mode Output Voltage
VCOM
VDD / 2
V
Maximum REFP/REFN/COM
Source Current
ISOURCE
2mA
Maximum REFP/REFN/COM
Sink Current
ISINK
2mA
REFIN Input Current
-0.7
A
REFIN Input Resistance
500
k
Ω
DIGITAL INPUTS (CLK, SCLK, DIN,
CS, D0–D9, T/R, SHDN)
Input High Threshold
VINH
0.7 x OVDD
V
Input Low Threshold
VINL
0.3 x OVDD
V
Input Leakage
DIIN
D0–D9, CLK, SCLK, DIN,
CS, T/R,
SHDN = OGND or OVDD
-1
+1
A
Input Capacitance
DCIN
5pF
DIGITAL OUTPUTS (D0–D9, DOUT)
Output-Voltage Low
VOL
ISINK = 200A
0.2 x OVDD
V
Output-Voltage High
VOH
ISOURCE = 200A
0.8 x OVDD
V
Tri-State Leakage Current
ILEAK
-1
+1
A
Tri-State Output Capacitance
COUT
5pF
Note 1: Specifications from TA = +25°C to +85°C are guaranteed by production tests. Specifications from TA = +25°C to -40°C are
guaranteed by design and characterization.
Note 2: Guaranteed by design and characterization.
Note 3: The minimum clock frequency (fCLK) for the MAX19708 is 1.5MHz (typ). The minimum aux-ADC sample rate clock frequen-
cy (ACLK) is determined by fCLK and the chosen aux-ADC clock-divider value. The minimum aux-ADC ACLK > 1.5MHz /
128 = 11.7kHz. The aux-ADC conversion time does not include the time to clock the serial data out of the SPI. The maximum
conversion time (for no averaging, NAVG = 1) will be tCONV (max) = (12 x 1 x 128) / 1.5MHz = 1024s.
Note 4: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude
of the digital outputs. SINAD and THD are calculated using HD2 through HD6.
Note 5: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the second
channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second channel
FFT test tone.
Note 6: Amplitude and phase matching is measured by applying the same signal to each channel, and comparing the two output
signals using a sine-wave fit.
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