參數(shù)資料
型號: MAX194BEWE+T
廠商: Maxim Integrated Products
文件頁數(shù): 24/24頁
文件大小: 0K
描述: IC ADC 14BIT 85KSPS 16-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 14
采樣率(每秒): 85k
數(shù)據(jù)接口: QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 80mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC W
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)單端,單極;1 個(gè)單端,雙極
If you read the data bits between conversions, you can
1) count CLK cycles until the end of the conversion, or
2) poll EOC to determine when the conversion is
finished, or
3) generate an interrupt on EOC’s falling edge.
Note that the MSB conversion result appears at DOUT
after CS goes low but before the first SCLK pulse. Each
subsequent SCLK pulse shifts out the next conversion
bit. The 15th SCLK pulse shifts out the sub-LSB (S0).
Additional clock pulses shift out zeros.
Data is clocked out on SCLK’s falling edge. Clock data
in on SCLK’s rising edge or, for clock speeds above
2.5MHz, on the following falling edge to meet the maxi-
mum SCLK-to-DOUT timing specification (Figure 7).
The maximum SCLK speed is 5MHz. See the
Operating
Modes and SPI/QSPI Interfaces section for additional
information. When the conversion clock is near its maxi-
MAX194
14-Bit, 85ksps ADC with 10A Shutdown
_______________________________________________________________________________________
9
CLK
START
CONV
MAX194
CONV
START
CLK
SEE
DIGITAL INTERFACE SECTION
CS
CONV
CLK
(CASE 1)
CLK
(CASE 2)
EOC
tDV
tCD
tCW
tCEH
CASE 1: CLK IDLES LOW, DATA LATCHED ON RISING EDGE (CPOL = 0, CPHA = 0)
CASE 2: CLK IDLES LOW, DATA LATCHED ON FALLING EDGE (CPOL = 0, CPHA = 1)
NOTE: ARROWS ON CLK TRANSITIONS INDICATE LATCHING EDGE
tCEL
DOUT
tDH
B13
CONVERSION
BEGINS
CONVERSION
ENDS
MSB
LSB
SUB-LSBs
B12
B11
B10
B0
S1
S0
B13
B13 FROM PREVIOUS
CONVERSION
Figure 5. Gating CONV to Synchronize with CLK
Figure 6. Output Data Format, Reading Data During Conversion (Mode 1)
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