參數(shù)資料
型號: MAX194BEWE+T
廠商: Maxim Integrated Products
文件頁數(shù): 2/24頁
文件大?。?/td> 0K
描述: IC ADC 14BIT 85KSPS 16-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1,000
位數(shù): 14
采樣率(每秒): 85k
數(shù)據(jù)接口: QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 80mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC W
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個單端,單極;1 個單端,雙極
MAX194
mum (1.7MHz), reading the data after each conversion
(during the acquisition time) results in lower throughput
(about 70ksps max) than reading the data during con-
versions, because it takes longer than the minimum
input acquisition time (four cycles at 1.7MHz) to clock
16 data bits at 5Mbps. After the data has been clocked
in, leave some time (about 1s) for any coupled noise
on AIN to settle before beginning the next conversion.
Whichever method is chosen for reading the data, con-
versions can be individually initiated by bringing CONV
low, or they can occur continuously by connecting EOC
to CONV. Figure 8 shows the MAX194 in its simplest
operational configuration.
14-Bit, 85ksps ADC with 10A Shutdown
10
______________________________________________________________________________________
EOC
CS
SCLK
(CASE 1)
SCLK
(CASE 2)
CASE 1: SCLK IDLES LOW, DATA LATCHED ON RISING EDGE (CPOL = 0, CPHA = 0)
CASE 2: SCLK IDLES LOW, DATA LATCHED ON FALLING EDGE (CPOL = 0, CPHA = 1)
CASE 3: SCLK IDLES HIGH, DATA LATCHED ON FALLING EDGE (CPOL = 1, CPHA = 0)
NOTE: ARROWS ON SCLK TRANSITIONS INDICATE LATCHING EDGE
DOUT
SCLK
(CASE 3)
tCONV
tDH
tSD
tDV
MSB
LSB
SUB-LSBs
B13
B12
B11
B10
B1
B0
S1
S0
B9
tCSS
tCSH
MAX194
10
F
BP/UP/SHDN
CLK
SCLK
VDDD
DOUT
DGND
REFERENCE (0V TO VDDA)
ANALOG INPUT
-5V
EOC
CS
VDDA
VSSA
AGND
AIN
CONVERSION CLOCK
+5V
REF
VSSD
RESET
CONV
0.1
F
10
F
0.1
F
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Figure 7. Output Data Format, Reading Data Between Conversions (Mode 2)
Figure 8. MAX194 in the Simplest Operating Configuration
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