參數(shù)資料
型號: MAX191BCWG+T
廠商: Maxim Integrated Products
文件頁數(shù): 22/24頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 100KSPS 24-SOIC
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1,000
位數(shù): 12
采樣率(每秒): 100k
數(shù)據(jù)接口: MICROWIRE?,并聯(lián),QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 941mW
電壓電源: 雙 ±
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 24-SOIC W
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,單極;2 個單端,雙極;1 個差分,單極;1 個差分,雙極
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
_______________________________________________________________________________________
7
Pin Description
Clock Input/Serial Clock Input in serial mode. An external TTL-/CMOS-compatible clock may be applied to
this pin, or a capacitor (120pF nominal) may be connected between CLK and DGND to operate the internal
oscillator.
High-Byte Enable Input. In parallel mode, HBEN = high multiplexes the 4 MSBs of the conversion result
into the lower bit outputs. HBEN = high also disables conversion starts. HBEN = low places the 8 LSBs
onto the data bus. In serial mode, HBEN = low enables SCLKOUT to operate during the conversion only,
HBEN = high enables SCLKOUT to operate continuously, provided CS is low.
Chip-Select Input must be low for the ADC to recognize RD and HBEN inputs in parallel mode. The falling
edge of CS starts a conversion in serial mode. CS = high in serial mode forces SCLKOUT, SSTRB, and
DOUT into a high-impedance state.
Read Input. In parallel mode, a low signal starts a conversion when CS and HBEN are low (memory
mode). RD also enables the outputs when CS is low. In serial mode, RD = low enables SCLKOUT and
SSTRB when CS is low. RD = high forces SCLKOUT and SSTRB into a high-impedance state.
D6/SCLKOUT
7
Analog Ground
AGND
24
Positive Supply, +5V ±5%
VDD
23
CLK/SCLK
22
Sets the output mode. PAR = high selects parallel output mode. PAR = low selects serial output mode.
PAR
21
HBEN
20
CS
19
RD
18
Three-State Data Output/Data Output in serial mode
D7/DOUT
13
Three-State Data Outputs
D2/D10
14
Three-State Data Outputs: MSB = D11
D3/D11
15
Three-State Data Output
D4
16
Three-State Data Output/Serial Strobe Output in serial mode
D5/SSTRB
17
Three-State Data Output/Serial Clock Output in serial mode
10
Three-State Data Outputs: LSB = D0
D0/D8
11
Three-State Data Outputs
D1/D9
12
Digital Ground
DGND
Power-Down Input. A logic low at PD deactivates the ADC—only the bandgap reference is active. A logic
high selects normal operation, internal-reference compensation mode. An open-circuit condition selects
normal operation, external-reference compensation mode.
PIN
9
8
6
BUSY Output is low during a conversion.
BUSY
BIP = low selects unipolar mode
BIP = high selects bipolar mode (see
Gain and Offset Adjustment section)
BIP
5
4
3
Reference Adjust. Connect to VDD to use an extended reference at VREF.
REFADJ
Reference-Buffer Output for Internal Reference. Input for external reference when REFADJ is connected to
VDD.
VREF
Analog Input Return. Pseudo-differential (see
Gain and Offset Adjustment section).
AIN-
2
1
Sampled Analog Input
AIN+
Negative Supply, 0V to -5.25V
VSS
PD
FUNCTION
NAME
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