參數(shù)資料
型號(hào): MAX191BCWG+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 10/24頁(yè)
文件大小: 0K
描述: IC ADC 12BIT 100KSPS 24-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 12
采樣率(每秒): 100k
數(shù)據(jù)接口: MICROWIRE?,并聯(lián),QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 941mW
電壓電源: 雙 ±
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SOIC W
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)單端,單極;2 個(gè)單端,雙極;1 個(gè)差分,單極;1 個(gè)差分,雙極
MAX191
Following the data transfer, the DSP receive shift regis-
ter (RSR) contains a 16-bit word consisting of the 12
data bits, MSB first, followed by four trailing 0s.
Applications Information
Power-On Initialization
When the +5V power supply is first applied to the
MAX191, perform a single conversion to initialize the
ADC (the BUSY signal status is undefined at power-on).
Disregard the data outputs.
Power-Down Mode
In some battery-powered systems, it is desirable to
power down or remove power from the ADC during
inactive periods. To power down the MAX191, drive PD
low. In this mode, all internal ADC circuitry is off except
the reference, and the ADC consumes less than 50A
max (assuming all signals CS, RD, CLK, and HBEN are
static and within 200mV of the supplies). Figure 17
shows a practical way to drive the PD pin. If using inter-
nal reference compensation, drive PD between VDD
and DGND with a P I/O pin or other logic device
(Figure 17a). For external-reference compensation
mode, use the circuit in Figure 17b to drive PD between
DGND and the floating voltage of PD. An alternative is
to drive PD with three-state logic or a switch, provided
the off leakage does not exceed 100nA.
Internal Reference
The internal 4.096V reference is available at VREF and
must be bypassed to AGND with a 4.7F low-ESR
capacitor (less than 1/2
) in parallel with a 0.1F capaci-
tor, unless internal-reference compensation mode is
used (see the
Internal Reference Compensation section).
This minimizes noise and maintains a low reference
impedance at high frequencies. The reference output
can be disabled by connecting REFADJ to VDD when
using an external reference.
Reference-Compensation Modes
Power-down performance can be optimized for a given
conversion rate by selecting either internal or external
reference compensation.
Internal Compensation
The connection for internal compensation is shown in
Figure 18a. In this mode, the reference stabilizes quick-
ly enough so that a conversion typically starts within
35s after the ADC is reactivated (PD pulled high). In
this compensation mode, the reference buffer requires
longer recovery time from SAR transients, therefore
requiring a slower clock (and conversion time). With
internal reference compensation, the typical conversion
time rises to 25s (Figure 18b). Figure 18c illustrates
the typical average supply current vs. conversion rate,
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
18
______________________________________________________________________________________
MAX191
a. INTERNAL-REFERENCE COMPENSATION MODE
b. EXTERNAL-REFERENCE COMPENSATION MODE
PD
1
PD
OPEN-DRAIN
BUFFER
Figure 17. Drive Circuits for PD Pin
MAX191
+5V
PD
VREF
REFADJ
0.1
F
1
5
6
Figure 18a. Internal-Compensation Mode Circuit
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