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參數(shù)資料
| 型號： | MAX19005CCS+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 14/25頁 |
| 文件大小： | 0K |
| 描述： | IC DCL QUAD 300MHZ ATE 80TQFP |
| 標準包裝： | 1,000 |
| 系列： | ATE |
| 邏輯類型： | 比較器, 驅動器 |
| 電源電壓： | -1 V ~ 5.2 V |
| 位數(shù)： | 4 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應商設備封裝： | * |
| 包裝： | * |
Maxim Integrated Products 21
MAX19005
Quad, Ultra-Low-Power,
200Mbps ATE Drivers/Comparators
Passive Load
The IC channels each feature a passive load consisting
of a buffered input voltage (LDV_) connected to DUT_
through two resistive paths (Figure 2). Each path con-
nects to DUT_ individually by a switch controlled through
the serial interface. Programming options include none
(load disconnected), either, or both paths connected.
The loads facilitate fast open/short testing in conjunction
with the comparator, and pullup of open-drain DUT_ out-
puts. See Table 3.
Parametric Switches
Each of the four IC channels provide force-and-sense
paths for connection of a PMU or other DC resource to
the device-under-test (Figure 2). Both force and sense
switches are simultaneously controlled through the serial
interface providing maximum application flexibility. PMU_
and DUT_ are provided on separate pins, allowing
designs that do not require the parametric switch feature
to avoid the added capacitance of PMU_. It also allows
PMU_ to connect to DUT_, either directly or with an
impedance-matching network. See Table 4.
Low-Leakage Mode (LLEAK_)
Asserting LLEAK_ through the serial port places the
IC into a very-low-leakage state. See the Electrical
Characteristics section. This mode is convenient for mak-
ing IDDQ and PMU measurements without the need for
an output disconnect relay. LLEAK_ control is indepen-
dent for each channel.
When DUT_ is driven with a high-speed signal while
LLEAK_ is asserted, the leakage current momentari-
ly increases beyond the limits specified for normal
operation. The low-leakage recovery specification in
the Electrical Characteristics section indicates device
behavior under this condition.
X = Don’t care.
Table 4. PMU Switch Logic
Table 3. Passive Load Logic
Figure 4. Complementary 50I Comparator Outputs
Table 2. Comparator Logic
INTERNAL CONTROL BITS
PASSIVE LOAD
STATUS
LOAD EN
HIGH
LOAD EN
LOW
0
Disconnect
0
1
375I load connect
1
0
750I load connect
1
750I || 375I
load connect
EXTERNAL
CONNECTION
INTERNAL
CONTROL BIT
PMU SWITCH
STATUS
SWEN
PMU EN
0
X
Open
1
0
Open
1
Short
CONDITION
CMPH
CMPL
DUT_ < CHV_
DUT_ < CLV_
0
DUT_ < CHV_
DUT_ > CLV_
0
1
DUT_ > CHV_
DUT_ < CLV_
1
0
DUT_ > CHV_
DUT_ > CLV_
1
COMPHI
CHV_
DUT_
CLV_
COMPLO
50I
CMPH_
50I
CMPL_
VBBO
MAX19005
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