參數(shù)資料
型號(hào)： MAX15501GTJ+T
廠(chǎng)商： Maxim Integrated Products
文件頁(yè)數(shù)： 26/28頁(yè)
文件大?。?/td> 0K
描述： IC COND ANLG OUTPUT 2.5V 32TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
類(lèi)型： 調(diào)節(jié)器
數(shù)據(jù)接口： 串行，SPI?
電壓電源： 模擬和數(shù)字，雙 ±
電源電壓： ±24V，2.7 V ~ 5.25 V
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 32-TQFN-EP（5x5）
包裝： 帶卷 (TR)
Industrial Analog Current/
Voltage-Output Conditioners
MAX15500/MAX15501
_______________________________________________________________________________________ 7
Note 1: Use diodes as shown in the Typical Operating Circuit/Functional Diagram to ensure a voltage difference of 2V to 3.5V
from AVDD to AVDDO and from AVSS to AVSSO.
Note 2: RLOAD = 750I. For the MAX15500, RSENSE = 48.7I for FSMODE = DVDD and RSENSE = 42.2I for FSMODE = DGND.
For the MAX15501, RSENSE = 47.3I for FSMODE = DVDD and RSENSE = 41.2I for FSMODE = DGND. See the Typical
Operating Circuit/Functional Diagram.
Note 3: Condition at which part is stable.
Note 4: The maximum clock speed for daisy-chain applications is 10MHz.
Note 5: tCSH is applied to CS_ falling to determine the 1st SCLK falling edge in a free-running SCLK application. It is also applied
to CS_ rising with respect to the 15th SCLK falling edge to determine the end of the frame.
Note 6: After the 14th SCLK falling edge, the MAX15500/MAX15501 outputs are high impedance and DOUT data is ignored.
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +24V, VAVSS = -24V, VDVDD = 5.0V, CLOAD = 1nF, CCOMP = 0nF, VREFIN = 4.096V for the MAX15500, VREFIN = 2.5V for
the MAX15501. All specifications for TA = -40NC to +105NC. Typical values are at TA = +25NC, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS
Serial-Clock Frequency
fSCLK
(Note 4)
0
20
MHz
SCLK Pulse-Width High
tCH
40% duty cycle
20
ns
SCLK Pulse-Width Low
tCL
60% duty cycle
20
ns
CS_ Fall to SCLK Fall Setup Time
tCSS
To 1st SCLK falling edge
15
ns
SCLK Fall to CS_ Fall Hold Time
tCSH
(Note 5)
0
ns
DIN to SCLK Fall Setup Time
tDS
15
ns
DIN to SCLK Fall Hold Time
tDH
0
ns
SCLK Fall to DOUT Settle Time
tDOT
CLOAD = 20pF
30
ns
SCLK Fall to DOUT Hold Time
tDOH
CLOAD = 0pF
2
ns
SCLK Fall to DOUT Disable
tDOZ
14th SCLK deassertion (Note 6)
30
ns
SCLK Fall to READY Fall
tCR
16th SCLK assertion, CLOAD = 0pF or 20pF
2
30
ns
CS_ Fall to DOUT Enable
tDOE
Asynchronous assertion
1
35
ns
CS_ Rise to DOUT Disable
tCSDOZ
Asynchronous deassertion
35
ns
CS_ Rise to READY Rise
tCSR
Asynchronous deassertion, CLOAD = 20pF
35
ns
CS_ Pulse-Width High
tCSW
15
ns
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