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參數(shù)資料
| 型號： | MAX145BEUA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 16/16頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 108KSPS 8-UMAX |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 108k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 330mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個偽差分，單極 |
Selecting Clock Mode
To start the conversion process on the MAX144/
MAX145, pull CS/SHDN low. At CS/SHDN’s falling
edge, the part wakes up and the internal T/H enters
track mode. In addition, the state of SCLK at
CS/SHDN’s falling edge selects internal (SCLK = high)
or external (SCLK = low) clock mode.
Internal Clock (fSCLK < 100kHz or fSCLK > 2.17MHz)
In internal clock mode, the MAX144/MAX145 run from
an internal, laser-trimmed oscillator to within 20% of the
2MHz specified clock rate. This releases the system
microprocessor from running the SAR conversion clock
and allows the conversion results to be read back at
the processor’s convenience, at any clock rate from 0
to 5MHz. Operating the MAX144/MAX145 in internal
clock mode is necessary for serial interfaces operating
with clock frequencies lower than 100kHz or greater
than 2.17MHz. Select internal clock mode (Figure 5), by
holding SCLK high during a high/low transition of
CS/SHDN. The first SCLK falling edge samples the data
and initiates a conversion using the integrated on-chip
oscillator. After the conversion, the oscillator shuts off
and DOUT goes high, signaling the end of conversion
(EOC). Data can then be read out with SCLK.
External Clock (fSCLK = 100kHz to 2.17MHz)
The external clock mode (Figure 6) is selected by tran-
sitioning CS/SHDN from high to low while SCLK is low.
The external clock signal not only shifts data out, but
also drives the analog-to-digital conversion. The input
is sampled and conversion begins on the falling edge
of the second clock pulse. Conversion must be com-
pleted within 140s to prevent degradation in the con-
version results caused by droop on the T/H capacitors.
External clock mode provides the best throughput for
clock frequencies between 100kHz and 2.17MHz.
Output Data Format
Table 1 illustrates the 16-bit, serial data stream output
format for both the MAX144 and MAX145. The first
three bits are always logic high (including the EOC bit
for internal clock mode), followed by the channel identi-
fication (CHID = 0 for CH0, CHID = 1 for CH1, CHID = 0
for the MAX145), and then 12 bits of data in MSB-first
format. After the last bit has been read out, additional
SCLK pulses will clock out trailing zeros. DOUT transi-
tions on the falling edge of SCLK. The output remains
high-impedance when CS/SHDN is high.
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin MAX
_______________________________________________________________________________________
9
DOUT
D9
D10
MSB
CHID
1
EOC
SAMPLING INSTANT
HIGH-Z
D8
D7
D6
D5
D4
D3
D2
D1
D0
HIGH-Z
SCLK
678
9
10
11
12
3
4
5
12
13
14
15
16
tCONV
tWAKE
(tACQ)
tCS
POWER
DOWN
ACTIVE
CS/SHDN
Figure 5. Internal Clock Mode Timing
DOUT
D9
D10
MSB
CHID
SAMPLING INSTANT
HIGH-Z
D8
D7
D6
D5
D4
D3
D2
D1
D0
HIGH-Z
SCLK
678
9
10
11
12
3
4
5
12
13
14
15
16
tWAKE
(tACQ)
tCS
POWER
DOWN
ACTIVE
POWER
DOWN
ACTIVE
CS/SHDN
Figure 6. External Clock Mode Timing
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