參數(shù)資料
型號(hào)： MAX1459CAP+T
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： 2-Wire, 4-20mA Smart Signal Conditioner
中文描述： SPECIALTY ANALOG CIRCUIT, PDSO20
封裝： SSOP-20
文件頁(yè)數(shù)： 24/24頁(yè)
文件大?。?/td> 243K
代理商： MAX1459CAP+T
The offset TC DAC output is fed into the output sum-
ming junction where it is gained by approximately 2.3,
thereby increasing the offset TC correction range. The
buffered FSOTC DAC output is available at FSOTC and
is connected to ISRC via RFTC to correct FSOTC errors.
Internal Resistors
The MAX1459 contains three internal resistors (RISRC,
RFTC, and RTEMP) optimized for common silicon PRTs.
RISRC (in conjunction with the FSO DAC) programs the
nominal sensor excitation current. RFTC (in conjunction
with the FSOTC DAC) compensates the FSOTC errors.
Both RISRC and RFTC have a nominal value of 100k
. If
external resistors are used, RISRC and RFTC can be
disabled by setting the appropriate bit (address 07h
reset to zero) in the configuration register (Table 3).
RTEMP is a high-tempco resistor with a TC of
+4600ppm/°C and a nominal resistance of 100k
at
+25°C. This resistor can be used with certain sensor
types that require an external temperature sensor. The
two RTEMP terminals are available as pin 16 and pin 17
of the MAX1459.
Internal EEPROM
The MAX1459 has a 128-bit internal EEPROM arranged
as eight 16-bit registers. The 4 uppermost bits for each
register are reserved. The internal EEPROM is used to
store the following (also shown in the memory map in
Table 4):
Configuration register (Table 3)
12-bit calibration coefficients for the offset and FSO
DACs
12-bit compensation coefficients for the offset TC
and FSOTC DACs
Two general-purpose registers available to the user
for storing process information such as serial num-
ber, batch date, and check sums
The EEPROM is bit addressable. Program the EEPROM
using the following steps, where the bits have address-
es from 0 to 127 (07F hex):
1) Read the entire EEPROM, and temporarily store the
reserved bits.
2) Erase the entire EEPROM, which causes all bits to
be 0 (see the ERASE EEPROM Command section).
3) Program 1 to the required bits, including the reserved
bits (see the WRITE EEPROM BIT Command section).
4) Read the whole EEPROM, either with the READ EEP-
ROM BIT or with the READ EEPROM MATRIX com-
mands (see the READ EEPROM BIT Command and
READ EEPROM MATRIX Command sections).
Configuration Register
The configuration register (Table 3) determines the
PGA gain, the polarity of the offset and offset TC coeffi-
cients, and the coarse offset correction (IRO DAC). It
also enables/disables internal resistors (RFTC and
RISRC).
DAC Registers
The offset, offset TC, FSO, and FSOTC registers store
the coefficients used by their respective calibration/
compensation DACs.
Detailed Description of the Digital Lines
Chip-Select (CS) and Write-Enable (WE)
CS is used to enable OUT, control serial communica-
tion, and force an update of the configuration and DAC
registers:
A low on CS disables serial communication and
places OUT in a high-impedance state.
A transition from low to high on CS forces an update
of the configuration and DAC registers from the
MAX1459
2-Wire, 4–20mA
Smart Signal Conditioner
_______________________________________________________________________________________
9
Table 3. Configuration Register
Description
01
1
00
03
0
3
02
2
05
5
04
07
4
7
06
6
09
BIT
9
EEPROM
ADDRESS (hex)
08
0B
8
11
0A
10
Offset TC Sign Bit, SOTC
Offset Sign Bit, SOFF
PGA Gain (LSB), A0
PGA Gain, A1
PGA Gain (MSB), A2
Temperature Sensor Selection Bit
(0 = default VBDRIVE)
Reserved “0”
RISRC/RFTC Selection Bit
(0 = enable internal), IRS
IRO LSB, C0
IRO, C1
IRO MSB, C2
IRO Sign, SIRO
DESCRIPTION
CONFIGURATION REGISTER
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