參數(shù)資料
型號(hào): MAX1459CAP+T
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 模擬信號(hào)調(diào)理
英文描述: 2-Wire, 4-20mA Smart Signal Conditioner
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO20
封裝: SSOP-20
文件頁數(shù): 22/24頁
文件大?。?/td> 243K
代理商: MAX1459CAP+T
age is fed into the PGA. The 3-bit (plus sign) input-
referred offset DAC (IRO DAC) generates the coarse
offset-correction voltage. The DAC voltage reference is
1.25% of VDD; thus, a VDD of 5V results in a front-end
offset-correction voltage ranging from -63mV to +63mV,
in 9mV steps (Table 1). To add an offset to the input
signal, set the IRO sign bit high; to subtract an offset
from the input signal, set the IRO sign bit low. The IRO
DAC bits (C2, C1, C0, and IRO sign bit) are pro-
grammed in the configuration register (see Internal
EEPROM section).
Programmable-Gain Amplifier
The programmable-gain amplifier (PGA), which is used
to set the coarse FSO, uses a switched-capacitor
CMOS technology and contains eight selectable gain
levels from 41 to 230, in increments of 27 (Table 2). The
output of the PGA is fed to the output summing junc-
tion. The three PGA gain bits A2, A1, and A0 are stored
in the configuration register.
Output Summing Junction
The third stage in the analog signal path consists of a
summing junction for the PGA output, offset correction,
and the offset TC correction. Both the offset and the off-
set TC correction voltages are gained by a factor of 2.3
before being fed into the summing junction, increasing
the offset and offset TC correction range. The offset sign
bit and offset TC sign bit are stored in the configuration
register. The offset sign bit determines whether the off-
set correction voltage is added to (sign bit is high) or
subtracted from (sign bit is low) the PGA output.
Negative offset TC errors require a logic high for the off-
set TC sign bit. Alternately, positive offset TC errors dic-
tate a logic low for the offset TC sign bit. The output of
the summing junction is fed to the output buffer.
MAX1459
2-Wire, 4–20mA
Smart Signal Conditioner
_______________________________________________________________________________________
7
Figure 2. Bridge Excitation Circuit
VDD
AA
≈ 12IISRC = IBDRIVE
I = IISRC
ISRC
FSOTC
RISRC
BDRIVE
VDD
RFTC
EXTERNAL
SENSOR
FSO
DAC
FSOTC
DAC
SOTC
BDRIVE
1.25% VDD
SOFF
±
A2
INP
INM
A1 A0
PGA
Σ
A = 1
OUT
A = 2.3
OFFTC
DAC
IRO
DAC
VDD
OFFSET
DAC
Figure 3. Signal-Path Block Diagram
相關(guān)PDF資料
PDF描述
MAX1459AAP+T 2-Wire, 4-20mA Smart Signal Conditioner
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MAX1459AAP+ 2-Wire, 4-20mA Smart Signal Conditioner
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