參數(shù)資料
型號(hào): MAX1414CAI+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 46/48頁(yè)
文件大小: 0K
描述: IC DAS 16BIT LP 28-SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 46
類型: 數(shù)據(jù)采集系統(tǒng)(DAS)
分辨率(位): 16 b
采樣率(每秒): 60
數(shù)據(jù)接口: 串行
電壓電源: 模擬和數(shù)字
電源電壓: 2.7 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 28-SSOP
包裝: 管件
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
_______________________________________________________________________________________
7
Note 1: Single conversion.
Note 2: DNL and INL are measured between code 010hex and 3FFhex.
Note 3: Offset error is referenced to code 010hex.
Note 4: Output swing is a function of external gain-setting feedback resistors and REF voltage.
Note 5: Measured with no load on FOUT, DOUT, and the DAC amplifiers. SCLK is idle, and all digital inputs are at DGND or DVDD.
Note 6: SHDN stays high if the PLL is on.
Note 7: Actual worst-case performance is ±2.5LSB. Guaranteed limit of ±3.5LSB is due to production test limitation.
Note 8: Guaranteed by design. Not production tested.
TIMING CHARACTERISTICS (continued)
(MAX1407/MAX1408/MAX1409/MAX1414: AVDD = DVDD = 2.7V to 3.6V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TYPICAL TIMING PARAMETERS
OUT1/OUT2 Turn-Off Time
Input impedance > 1M
(MAX1407/MAX1409/MAX1414 only)
100
s
Sleep Voltage Monitor Timeout
Period
tDSLP
The delay for the sleep voltage monitor
output, RESET, to go high after AVDD rises
above the reset threshold (+1.8V when bit
VM = 1 and +2.7V, when bit VM = 0); this is
largely driven by the startup of the 32kHz
oscillator
1.54
s
WU1 or WU2 Pulse Width
tWU
Minimum pulse width required to detect a
wake-up event
1s
Shutdown Deassert Delay
tDPU
The delay for SHDN to go high after a valid
wake-up event
1s
FOUT Turn-On Time
tDFON
The turn-on time for the high-frequency
clock; it is gated by an AND function with
three signals—the RESET signal, the internal
low voltage VDD monitor signal, and the
assertion of the PLL; the time delay is timed
from when the low-voltage monitor trips or
the RESET going high, whichever happens
later; FOUT always starts in the low state
31.25
ms
INT Delay
tDFI
The delay for INT to go low after the FOUT
clock output has been enabled; INT is used
as an interrupt signal to inform the P the
high-frequency clock has started
7.82
ms
FOUT Disable Delay
tDFOF
The delay after a shutdown command has
asserted and before FOUT is disabled; this
gives the microcontroller time to clean up
and go into Sleep mode properly
1.95
ms
SHDN Assertion Delay
tDPD
The delay after a shutdown command has
asserted and before SHDN is pulled low
(turning off the DC-DC converter) (Note 6)
2.93
ms
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