參數(shù)資料
型號(hào)： MAX1414CAI+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 22/48頁(yè)
文件大小： 0K
描述： IC DAS 16BIT LP 28-SSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 46
類型： 數(shù)據(jù)采集系統(tǒng)（DAS）
分辨率（位）： 16 b
采樣率（每秒）： 60
數(shù)據(jù)接口： 串行
電壓電源： 模擬和數(shù)字
電源電壓： 2.7 V ~ 3.6 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 管件
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
______________________________________________________________________________________
29
WU2: Wake-Up2 status bit. When WU2 is pulled low,
WU2 is set to a logic 1. Reading the Status register
clears WU2, unless WU2 is still low. When WU2 is
pulled low when the device is awake (not in Sleep
mode), WU2 is cleared.
WU1: Wake-Up1 status bit. When WU1 is pulled low,
WU1 is set to a logic 1. Reading the Status register
clears WU1, unless WU1 is still low. When WU1 is
pulled low when the device is awake (not in Sleep
mode), WU1 is cleared.
RST: Reset status bit. When AVDD drops below the
RESET Voltage Monitor trip threshold (+1.8V or +2.7V),
RST is set to 1. This corresponds to the assertion of the
RESET pin. Reading the Status register clears RST,
unless AVDD is still below the RESET Voltage Monitor
trip threshold. At power-up, RST is at a logic 1 until the
Status register is read.
LVD: Low VDD status bit. When AVDD drops below the
Low VDD Voltage Monitor trip threshold (+2.7V), LVD is
set to a logic 1. Reading the Status register clears LVD
unless AVDD is still below 2.7V. At power-up, LVD is at
a logic 1 until the Status register is read. When the Low
VDD Voltage Monitor is powered down (LVDE = 0), the
LVD bit stays unchanged.
SDC: Signal-Detect Comparator status bit. SDC is set
to “1” when the differential polarity voltage across the
signal-detect comparator exceeds the signal-detect
threshold (0mV for the MAX1407/MAX1408/MAX1409
and 50mV for the MAX1414). This corresponds to the
assertion of the INT pin. Reading the Status register
clears SDC unless the condition remains true. SDC is
also reset to 0 when the signal-detect comparator is
powered down (SDCE = 0).
CLK: FOUT Clock Enable status bit. CLK is set to “1”
after the FOUT clock pin has been enabled in tDFON
milliseconds (see Figure 15). Reading the Status register
clears the CLK bit.
ADD: ADC Done Status bit. ADD is set to “1” to indicate
that the ADC has completed either a normal conversion
or a calibration conversion, and the conversion result is
available to be read. This corresponds to the assertion
of the DRDY pin. Reading either the Data or Offset
register clears the ADD bit. Reading the Status register
WILL NOT clear this bit.
Alarm Registers
The Al_Sec, Al_Min, Al_Hour, Al_Day registers are pro-
grammed through the serial port to store the preset
time data in binary-coded decimal format (BCD). See
Table 6 for decimal to BCD conversion. These registers
can be accessed individually or consecutively using
burst mode (see Al_Burst Register section).
To enable the alarm, set the AE bit of the
Alarm/Clock_Ctrl Register to 1 (see Alarm and RTC
Programming section). When an alarm occurs in any
mode, the ALIRQ bit of the AL_Status register will
change from 0 to 1, and the INT output will go low
unless you are in Sleep mode. If not already awake, the
device will wake-up from Sleep mode to Standby mode
and INT goes low when the PLL output is available. The
crystal oscillator, RTC, wake-up circuitry, reset voltage
monitor, low VDD voltage monitor (if applicable), and
the PLL are all powered up in standby mode.
Four alarm registers (Al_Sec, Al_Min, Al_Hour, and
Al_Day) are used to store the preset time value for the
alarm function. Bit 7 of the Al_Sec, Al_Min, Al_Hour,
Al_Day registers is the mask bit and is used to program
how often the alarm occurs. Table 7 shows how Bit 7 of
the four alarm registers should be set for the time of
day alarm to occur. Other combinations of mask bits
are possible to set different alarms.
FIRST BIT (MSB)
(LSB)
NAME
WU2
WU1
RST
LVD
SDC
CLK
ADD
—
DEFAULT
0
1
0
STATUS REGISTER (00110)
Table 6. BCD Conversion
DECIMAL DIGIT
BCD
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
UNUSED CODES
1010
1011
1100
1101
1110
1111
相關(guān)PDF資料
PDF描述
NBXDPA019LN1TAG IC CLK XO LVDS 125/250MHZ 6CLCC
MAX181CCQH+D IC DAS 12BIT 100KSPS 44-PLCC
74AC138SC IC DECODER/DEMUX 1OF8 16-SOIC
MAX181CCQH-D IC DAS 6CH 12BIT 100KHZ 44-PLCC
V110A48M300BL3 CONVERTER MOD DC/DC 48V 300W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX1414CAI+ 功能描述:ADC / DAC多通道 16-Bit 4Ch 60sps 1.35V Precision ADC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX1414CAI+T 功能描述:ADC / DAC多通道 16-Bit 4Ch 60sps 1.35V Precision ADC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX1414CAI-T 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX1414EAI 制造商:Maxim Integrated Products 功能描述:LOW-POWER, 16-BIT MULTICHANNEL DAS WITH INTER - Bulk
MAX1414EAI+ 制造商:Maxim Integrated Products 功能描述:LOW-POWER 16-BIT MULTICHANNEL DAS - Rail/Tube
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*