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參數(shù)資料
| 型號： | MAX1297BEEG+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 265KSPS 24-QSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 265k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 667mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-QSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極；2 個單端，雙極；1 個偽差分，單極；1 個偽差分，雙極 |
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
10
______________________________________________________________________________________
der of the conversion cycle to restore node ZERO to 0V
within the limits of 12-bit resolution. This action is equiv-
alent to transferring a 12pF (VIN+ - VIN-) charge from
CHOLD to the binary-weighted capacitive DAC, which in
turn forms a digital representation of the analog input
signal.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to VDD and GND, allow each input channel to
swing within (GND - 300mV) to (VDD + 300mV) without
damage. However, for accurate conversions near full
scale, both inputs must not exceed (VDD + 50mV) or be
less than (GND - 50mV).
If an analog input voltage exceeds the supplies by
more than 50mV, limit the forward-bias input current to
4mA.
Track/Hold
The MAX1295/MAX1297 T/H stage enters its tracking
mode on WR’s rising edge. In external acquisition
mode, the part enters its hold mode on the next rising
edge of WR. In internal acquisition mode, the part
enters its hold mode on the fourth falling edge of clock
after writing the control byte. Note that, in internal clock
mode, this is approximately 1s after writing the control
byte.
In single-ended operation, IN- is connected to COM
and the converter samples the positive “+” input. In
pseudo-differential operation, IN- connects to the nega-
tive “-” input, and the difference of |(IN+) - (IN-)| is sam-
pled. At the beginning of the next conversion, the
positive input connects back to IN+ and CHOLD
charges to the input signal.
The time required for the T/H stage to acquire an input
signal depends on how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time required for
the signal to be acquired. Calculate this with the follow-
ing equation:
tACQ = 9 (RS + RIN) CIN
where RS is the source impedance of the input signal,
RIN (800
) is the input resistance, and CIN (12pF) is
the input capacitance of the ADC. Source impedances
below 3k
have no significant impact on the MAX1295/
MAX1297’s AC performance.
Higher source impedances can be used if a 0.01F
capacitor is connected to the individual analog inputs.
A1
CH0
0
+
0
-
0
A0
0
1
CH2*
CH4*
+
-
0
1
0
+
CH3*
-
0
CH1
COM
1
CH5*
1
+
-
0
A2
+
-
1
0
1
-
+
1
Table 2. Channel Selection for Single-Ended Operation (SGL/DIF = 1)
Table 3. Channel Selection for Pseudo-Differential Operation (SGL/DIF = 0)
A1
CH0
0
+
0
-
0
A0
0
-
1
CH2*
CH4*
+
0
1
0
+
-
CH3*
0
CH1
1
CH5*
1
-
+
0
A2
+
-
1
0
1
-
+
1
*Channels CH2–CH5 apply to MAX1295 only.
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