參數(shù)資料
型號(hào): MAX1297BEEG+T
廠商: Maxim Integrated Products
文件頁數(shù): 18/19頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 265KSPS 24-QSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 12
采樣率(每秒): 265k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 667mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 24-QSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)單端,單極;2 個(gè)單端,雙極;1 個(gè)偽差分,單極;1 個(gè)偽差分,雙極
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
8
_______________________________________________________________________________________
Pin Description (continued)
PIN
MAX1297
REF
21
25
MAX1295
NAME
Bandgap Reference Buffer Output/External Reference Input. Add a 4.7F capacitor
to GND when using the internal reference.
FUNCTION
26
22
VDD
Analog +2.7V to +3.6V Power Supply. Bypass with a 0.1F capacitor to GND.
27
23
D11
Three-State Digital Output (D11)
28
24
D10
Three-State Digital Output (D10)
_______________Detailed Description
Converter Operation
The MAX1295/MAX1297 ADCs use a successive-
approximation (SAR) conversion technique and an input
track/hold (T/H) stage to convert an analog input signal
to a 12-bit digital output. This output format provides an
easy interface to standard microprocessors (Ps). Figure
2 shows the simplified internal architecture of the
MAX1295/MAX1297.
Single-Ended and
Pseudo-Differential Operation
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit in
Figure 3. In single-ended mode, IN+ is internally
switched to channels CH0–CH5 for the MAX1295
(Figure 3a) and to CH0–CH1 for the MAX1297 (Figure
3b), while IN- is switched to COM (Table 2). In differen-
tial mode, IN+ and IN- are selected from analog input
pairs (Table 3) and are internally switched to either of
T/H
THREE-STATE, BIDIRECTIONAL
I/O INTERFACE
12
17k
12
SUCCESSIVE-
APPROXIMATION
REGISTER
CHARGE REDISTRIBUTION
12-BIT DAC
CLOCK
ANALOG
INPUT
MULTIPLEXER
CONTROL LOGIC
&
LATCHES
REF
REFADJ
1.22V
REFERENCE
D0–D11
12-BIT DATA BUS
(CH5)
(CH4)
(CH3)
(CH2)
CH1
CH0
COM
CLK
CS
WR
RD
INT
( ) ARE FOR MAX1295 ONLY.
VDD
GND
MAX1295
MAX1297
AV =
2.05
COMP
Figure 2. Simplified Functional Diagram of 6-/2-Channel MAX1295/MAX1297
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