參數(shù)資料
型號(hào): MAX1246BEEE+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 10/25頁(yè)
文件大小: 0K
描述: IC ADC 12BIT SERIAL 16-QSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 12
采樣率(每秒): 133k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 667mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-QSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個(gè)單端,單極;4 個(gè)單端,雙極;2 個(gè)差分,單極;2 個(gè)差分,雙極
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
18
______________________________________________________________________________________
Figure 12. Average Supply Current vs. Conversion Rate with
External Reference
1000
10,000
0.1
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE
WITH EXTERNAL REFERENCE
100
10
1
CONVERSION RATE (Hz)
I
DD
(A)
1
100
10
1k
10k
1M
100k
MAX1247-12
VREF = VDD = 3.0V
RLOAD =
CODE = 101010100000
1 CHANNEL
4 CHANNELS
Figure 13b. MAX1246 Supply Current vs. Conversion Rate,
FASTPD
10,000
1
0.1
1
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE
(USING FASTPD)
1000
100
10
CONVERSION RATE (Hz)
I DD
(
A)
100
1M
10
1k
10k
100k
MAX1247-F13B
RLOAD =
CODE = 101010100000
4 CHANNELS
1 CHANNEL
Figure 13a. MAX1246 Supply Current vs. Conversion Rate,
FULLPD
100
1
0.01
0.1
1
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE
(USING FULLPD)
10
CONVERSION RATE (Hz)
AVERAGE
SUPPLY
CURRENT
(
A)
100
10
1k
MAX1247-F13A
RLOAD =
CODE = 101010100000
4 CHANNELS
1 CHANNEL
Figure 13c. Typical Reference-Buffer Power-Up Delay vs. Time
in Shutdown
2.0
0.0
0.001
0.01
0.1
1
10
TYPICAL REFERENCE-BUFFER POWER-UP
DELAY vs. TIME IN SHUTDOWN
1.5
1.0
0.5
TIME IN SHUTDOWN (sec)
POWER-UP
DELAY
(msec)
MAX1247-F13C
Power-Down Sequencing
The MAX1246/MAX1247 auto power-down modes can
save considerable power when operating at less than
maximum sample rates. Figures 12, 13a, and 13b show
the average supply current as a function of the sam-
pling rate. The following discussion illustrates the vari-
ous power-down sequences.
Lowest Power at up to 500
Conversions/Channel/Second
The following examples show two different power-down
sequences. Other combinations of clock rates, compen-
sation modes, and power-down modes may give lowest
power consumption in other applications.
Figure 13a depicts the MAX1246 power consumption
for one or four channel conversions utilizing full power-
down mode and internal-reference compensation. A
0.047F bypass capacitor at REFADJ forms an RC filter
with the internal 20k
reference resistor with a 0.9ms
time constant. To achieve full 12-bit accuracy, 10 time
constants or 9ms are required after power-up. Waiting
this 9ms in FASTPD mode instead of in full power-up
can reduce power consumption by a factor of 10 or
more. This is achieved by using the sequence shown in
Figure 14.
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