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參數(shù)資料
| 型號： | MAX1205CMH |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | +5v sINGLE-sUPPLY, 1mSPS, 14-bIT sELF-cALIBRATING adc |
| 中文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44 |
| 封裝： | M0-108AA-2, MQFP-44 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 127K |
| 代理商： | MAX1205CMH |
M
+5V S ingle-S upply, 1Msps, 14-Bit
S elf-Calibrating ADC
_______________________________________________________________________________________
7
Pin Desc ription (c ontinued)
PIN
25
26
Test Pin 2.
Leave unconnected.
Test Pin 1.
Leave unconnected.
TEST2
TEST1
FUNCTION
NAME
Digital Power Supply, +3V to +5.25V
Input Clock. Receives power from AV
DD
to reduce jitter.
DV
DD
CLK
27, 30
31
Data Valid Clock Output. This clock can be used to transfer the data to a memory or any other
data-acquisition system.
DAV
32
Test Pin 0.
Leave unconnected.
Common-Mode Voltage. Analog Input. Drive midway between positive and negative reference voltages.
TEST0
CM
34
35
Output Enable Input.
OE = 0: D0-D13 and DOR are high impedance.
OE = 1: All bits are active.
OE
33
Positive Reference Voltage. Force input.
Positive Reference Voltage. Sense input.
RFPF
RFPS
36
37
Negative Reference Voltage. Force input.
Negative Reference Voltage. Sense input.
RFNF
RFNS
38
39
Not Connected. No internal connection.
Negative Input Voltage
N.C.
INN
41, 42
43
Positive Input Voltage
INP
40
Digital Output for End of Calibration.
END_CAL = 0: Calibration in progress.
END_CAL = 1: Normal conversion mode.
END_CAL
44
_______________Detailed Desc ription
Converter Operation
The MAX1205 is a 14-bit, monolithic, analog-to-digital
converter (ADC) capable of conversion rates up to
1Msps. It uses a multistage, fully differential pipelined
architecture with digital error correction and self-cali-
bration to provide typically greater than 91dB spurious-
free dynamic range at a 1Msps sampling rate. Its
signal-to-noise ratio, harmonic distortion, and intermod-
ulation products are also consistent with 14-bit accura-
cy up to the Nyquist frequency. This makes the device
suitable for applications such as imaging, scanners,
data acquisition, and digital communications.
Figure 1 shows the simplified, internal structure of the
ADC. A switched-capacitor pipelined architecture is
used to digitize the signal at a high throughput rate.
The first four stages of the pipeline use a low-resolution
quantizer to approximate the input signal. The multiply-
ing digital-to-analog converter (MDAC) stage is used to
subtract the quantized analog signal from the input.
The residue is then amplified with a fixed gain and
passed on to the next stage. The accuracy of the con-
verter is improved by a digital calibration algorithm
which corrects for mismatches between the capacitors
in the switched capacitor MDAC. Note that the pipeline
introduces latency of four sampling periods between
the input being sampled and the output appearing at
D13–D0.
While the device can handle both single-ended and dif-
ferential inputs (see
Requirements for Reference and
Analog Signal Inputs), the latter mode of operation will
guarantee best THD and SFDR performance. The dif-
ferential input provides the following advantages com-
pared to a single-ended operation:
Twice as much signal input span
Common-mode noise immunity
Virtual elimination of the even-order harmonics
Less stringent requirements on the input signal
processing amplifiers
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| MAX1205CMH+ | 制造商:Maxim Integrated Products 功能描述:ADC SGL PIPELINED 1MSPS 14BIT PARALLEL 44MQFP - Rail/Tube |
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