參數(shù)資料
型號(hào): MAX1204BMJP
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: 5v, 8-cHANNEL, sERIAL, 10-bIT adc WITH 3v dIGITAL iNTERFACE
中文描述: 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20
封裝: 0.300 INCH, CERDIP-20
文件頁(yè)數(shù): 19/24頁(yè)
文件大?。?/td> 170K
代理商: MAX1204BMJP
M
5V, 8-Channel, S erial, 10-Bit ADC
with 3V Digital Interfac e
______________________________________________________________________________________
19
Figure 17, the Reference-Adjust Circuit, shows how to
adjust ADC gain in applications that use the internal
reference. The circuit provides ±1.5% (±16LSBs) of
gain-adjustment range.
Layout, Grounding, Bypassing
For best performance, use printed circuit boards.
Wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another, or digital
lines underneath the ADC package.
Figure 18 shows the recommended system-ground con-
nections. Establish a single-point analog ground (star
ground point) at GND. Connect all other analog grounds
to this ground. No other digital system ground should be
connected to this single-point analog ground. The
ground return to the power supply should be low imped-
ance and as short as possible for noise-free operation.
High-frequency noise in the V
DD
power supply may affect
the high-speed comparator in the ADC. Bypass these
supplies to the single-point analog ground with 0.1μF and
4.7μF bypass capacitors close to the MAX1204. Minimize
capacitor lead lengths for best supply-noise rejection. If
the +5V power supply is very noisy, a 10
resistor can
be connected as a lowpass filter, as shown in Figure 18.
3.0
2.5
2.0
1.5
1.0
0.5
0
0.0001
0.001
0.01
0.1
1
10
TIME IN SHUTDOWN (sec)
P
Figure 14c. Typical Power-Up Delay vs. Time in Shutdown
Figure 14a. MAX1204 Supply Current vs. Sample Rate/Second,
FULLPD, 400kHz Clock
1000
1
0
100
300
500
FULL POWER-DOWN
10
100
M
CONVERSIONS PER CHANNEL PER SECOND
200
400
2ms FASTPD WAIT
400kHz EXTERNAL CLOCK
INTERNAL COMPENSATION
50
150
250
350
450
8 CHANNELS
1 CHANNEL
A
Figure 14b. MAX1204 Supply Current vs. Sample Rate/Second,
FASTPD, 2MHz Clock
10,000
10
0
FAST POWER-DOWN
100
1000
CONVERSIONS PER CHANNEL PER SECOND
2k
8 CHANNELS
1 CHANNEL
4k
6k
8k
10k
12k
14k
16k
18k
2MHz EXTERNAL CLOCK
EXTERNAL COMPENSATION
50μs WAIT
A
相關(guān)PDF資料
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