參數(shù)資料
型號(hào): MAX1202BEAP
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: 5v, 8-cHANNEL, sERIAL, 12-bIT adcS WITH 3v dIGITAL iNTERFACE
中文描述: 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝: 5.30 MM, 0.65 MM PITCH, PLASTIC, SSOP-20
文件頁(yè)數(shù): 9/24頁(yè)
文件大?。?/td> 309K
代理商: MAX1202BEAP
M
5V, 8-Channel, S erial, 12-Bit ADCs
with 3V Digital Interfac e
_______________________________________________________________________________________
9
_______________Detailed Desc ription
The MAX1202/MAX1203 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 12-bit digital output. A flexible ser-
ial interface provides easy interface to 3V microproces-
sors (μPs). Figure 3 is the MAX1202/MAX1203 block
diagram.
Pseudo-Differential Input
Figure 4 shows the ADC’s analog comparator’s sam-
pling architecture. In single-ended mode, IN+ is inter-
nally switched to CH0–CH7 and IN- is switched to
GND. In differential mode, IN+ and IN- are selected
from pairs of CH0/CH1, CH2/CH3, CH4/CH5, and
CH6/CH7. Configure the channels using Tables 3
and 4.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential such that only the signal at IN+ is
sampled. The return side (IN-) must remain stable (typi-
cally within ±0.5LSB, within ±0.1LSB for best results)
with respect to GND during a conversion. To do this,
connect a 0.1μF capacitor from IN- (of the selected
analog input) to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
HOLD
. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the input control word’s
last bit is entered. The T/H switch opens at the end of
the acquisition interval, retaining charge on C
HOLD
as a
sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching C
HOLD
from the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN- is sim-
ply GND. This unbalances node ZERO at the compara-
tor’s input. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 12-bit resolution.
This action is equivalent to transferring a charge of
16pF x [(V
IN
+) - (V
IN
-)] from C
HOLD
to the binary-
weighted capacitive DAC, which in turn forms a digital
representation of the analog input signal.
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
Figure 3. Block Diagram
+3.3V
3k
C
LOAD
GND
DOUT
C
LOAD
GND
3k
DOUT
a. High-Z to V
OH
and V
OL
to V
OH
b. High-Z to V
OL
and V
OH
to V
OL
+3.3V
3k
C
LOAD
GND
DOUT
C
LOAD
GND
3k
DOUT
a. V
OH
to High-Z
b. V
OL
to High-Z
INPUT
SHIFT
REGISTER
CONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
+2.44V
REFERENCE
(MAX1202)
T/H
ANALOG
INPUT
MUX
12-BIT
SAR
ADC
REF
IN
DOUT
SSTRB
V
DD
VL
V
SS
SCLK
DIN
CH0
CH1
CH2
CH3
CH4
CH7
GND
CH6
CH5
REFADJ
REF
OUT
CLOCK
+4.096V
20k
1.68
1
2
3
4
5
6
7
8
10
11
12
13
15
16
17
18
19
MAX1202
MAX1203
CS
SHDN
A
20
14
9
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MAX1202BEAP+T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 8Ch 133ksps 5V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1202BEAP-T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1202BEPP 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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