參數(shù)資料
型號(hào)： MAX1193ETI+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 8/26頁(yè)
文件大小： 0K
描述： IC ADC 8BIT 45MSPS DL 28-TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 8
采樣率（每秒）： 45M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 28-TQFN-EP（5x5）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個(gè)單端，雙極；2 個(gè)差分，雙極
MAX1193
provide lowest possible jitter. Any significant aperture
jitter would limit the SNR performance of the on-chip
ADCs as follows:
where fIN represents the analog input frequency and
tAJ is the time of the aperture jitter.
Clock jitter is especially critical for undersampling
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log input or other digital signal lines. The MAX1193
clock input operates with a VDD/2 voltage threshold
and accepts a 50% ±10% duty cycle (see Typical
Operating Characteristics).
System Timing Requirements
Figure 5 shows the relationship between the clock, ana-
log inputs, A/
B indicator, and the resulting output data.
Channel A (CHA) and channel B (CHB) are simultane-
ously sampled on the rising edge of the clock signal
(CLK) and the resulting data is multiplexed at the out-
put. CHA data is updated on the rising edge and CHB
data is updated on the falling edge of the CLK. The A/
B
indicator follows CLK with a typical delay time of 6ns
and remains high when CHA data is updated and low
when CHB data is updated. Including the delay
through the output latch, the total clock-cycle latency is
5 clock cycles for CHA and 5.5 clock cycles for CHB.
Digital Output Data (D0–D7),
Channel Data Indicator (A/
B
B)
D0–D7 and A/
B are TTL/CMOS-logic compatible. The
digital output coding is offset binary (Table 2, Figure 6).
The capacitive load on the digital outputs D0–D7
should be kept as low as possible (<15pF) to avoid
large digital currents feeding back into the analog por-
tion of the MAX1193 and degrading its dynamic perfor-
mance. Buffers on the digital outputs isolate them from
SNR
ft
IN
AJ
log
=×
××
×
20
1
2
π
Ultra-Low-Power, 45Msps, Dual 8-Bit ADC
16
______________________________________________________________________________________
tDOB
tCL
tCH
tCLK
tDOA
tDA/B
5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB)
A/B
CHB
D0–D7
D0B
CHA
D1A
CHB
D1B
CHA
D2A
CHB
D2B
CHA
D3A
CHB
D3B
CHA
D4A
CHB
D4B
CHA
D5A
CHB
D5B
CHA
D6A
CHB
D6B
CHA
CHB
CLK
Figure 5. System Timing Diagram
Figure 6. Transfer Function
INPUT VOLTAGE (LSB)
-1
-126 -125
256
2 x VREF
1LSB =
VREF = VREFP - VREFN
VREF
V
REF
V
REF
0+1
-127
+126
+128
+127
-128
+125
(COM)
OFFSET
BINAR
Y
OUTPUT
CODE
(LSB)
0000 0000
0000 0001
0000 0010
0000 0011
1111 1111
1111 1110
1111 1101
0111 1111
1000 0000
1000 0001
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