參數(shù)資料
型號: MAX1181ECM+D
廠商: Maxim Integrated Products
文件頁數(shù): 5/20頁
文件大?。?/td> 0K
描述: IC ADC 10BIT 80MSPS DUAL 48-TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 250
位數(shù): 10
采樣率(每秒): 80M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 291mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-TQFP 裸露焊盤(7x7)
包裝: 托盤
輸入數(shù)目和類型: 4 個單端,雙極;2 個差分,雙極
產(chǎn)品目錄頁面: 1396 (CN2011-ZH PDF)
______________________________________________________________________________________________________
13
of the MAX1181 small-series resistors (e.g., 100
Ω), add
to the digital output paths, close to the MAX1181.
Figure 4 displays the timing relationship between out-
put enable and data output valid, as well as power-
down/wake-up and data output valid.
Power-Down (PD) and Sleep
(SLEEP) Modes
The MAX1181 offers two power-save modes; sleep and
full power-down mode. In sleep mode (SLEEP = 1),
only the reference bias circuit is active (both ADCs are
disabled) and current consumption is reduced to
2.8mA.
To enter full power-down mode, pull PD high. With OE
simultaneously low, all outputs are latched at the last
value prior to the power-down. Pulling OE high, forces
the digital outputs into a high-impedance state.
Applications Information
Figure 5 depicts a typical application circuit containing
two single-ended to differential converters. The internal
reference provides a VDD / 2 output voltage for level-
shifting purposes. The input is buffered and then split
to a voltage follower and inverter. One lowpass filter per
ADC suppresses some of the wideband noise associat-
ed with high-speed operational amplifiers. The user
may select the RISO and CIN values to optimize the fil-
ter performance to suit a particular application. For the
application in Figure 5, a RISO of 50
Ω is placed before
the capacitive load to prevent ringing and oscillation.
MAX1181
Dual 10-Bit, 80Msps, 3V, Low-Power ADC
with Internal Reference and Parallel Outputs
DIFFERENTIAL INPUT
VOLTAGE*
DIFFERENTIAL INPUT
STRAIGHT OFFSET
BINARY
T/B = 0
TWO’S COMPLEMENT
T/B = 1
VREF 511/512
+FULL SCALE - 1LSB
11 1111 1111
01 1111 1111
VREF 1/512
+ 1 LSB
10 0000 0001
00 0000 0001
0
Bipolar Zero
10 0000 0000
00 0000 0000
-VREF 1/512
- 1 LSB
01 1111 1111
11 1111 1111
-VREF 511/512
- FULL SCALE + 1 LSB
00 0000 0001
10 0000 0001
-VREF 512/512
- FULL SCALE
00 0000 0000
10 0000 0000
Table 1. MAX1181 Output Codes For Differential Inputs
N - 6
N
N - 5
N + 1
N - 4
N + 2
N - 3
N + 3
N - 2
N + 4
N - 1
N + 5
N
N + 6
N + 1
5 CLOCK-CYCLE LATENCY
ANALOG INPUT
CLOCK INPUT
DATA OUTPUT
D9A–D0A
tD0
tCH
tCL
N - 6
N - 5
N - 4
N - 3
N - 2
N - 1
N
N + 1
DATA OUTPUT
D9B–D0B
tCLK
Figure 3. System Timing Diagram
*VREF = VREFP - VREFN
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