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參數(shù)資料
| 型號(hào)： | MAX1181ECM+D |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 2/20頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 80MSPS DUAL 48-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 291mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP 裸露焊盤(pán)（7x7） |
| 包裝： | 托盤(pán) |
| 輸入數(shù)目和類型： | 4 個(gè)單端，雙極；2 個(gè)差分，雙極 |
| 產(chǎn)品目錄頁(yè)面： | 1396 (CN2011-ZH PDF) |
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MAX1181
Detailed Description
The MAX1181 uses a nine-stage, fully-differential
pipelined architecture (Figure 1), that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half clock cycle.
Counting the delay through the output latch, the clock-
cycle latency is five clock cycles.
1.5-bit (two-comparator) flash ADCs convert the held-
input voltages into a digital code. The digital-to-analog
converters (DACs) convert the digitized results back
into analog voltages, which are then subtracted from
the original held-input signals. The resulting error sig-
nals are then multiplied by two, and the residues are
passed along to the next pipeline stages where the
process is repeated until the signals have been
processed by all nine stages. Digital error correction
compensates for ADC comparator offsets in each of
these pipeline stages and ensures no missing codes.
Input Track-and-Hold (T/H) Circuits
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuits in both track-and-
hold mode. In track mode, switches S1, S2a, S2b, S4a,
S4b, S5a and S5b are closed. The fully-differential cir-
cuits sample the input signals onto the two capacitors
(C2a and C2b) through switches S4a and S4b. S2a and
S2b set the common mode for the amplifier input, and
open simultaneously with S1, sampling the input wave-
form. Switches S4a and S4b are then opened before
switches S3a and S3b connect capacitors C1a and
C1b to the output of the amplifier and switch S4c is
closed. The resulting differential voltages are held on
capacitors C2a and C2b. The amplifiers are used to
charge capacitors C1a and C1b to the same values
originally held on C2a and C2b. These values are then
presented to the first-stage quantizers and isolate the
pipelines from the fast-changing inputs. The wide input
bandwidth T/H amplifiers allow the MAX1181 to track
and sample/hold analog inputs of high frequencies
(> Nyquist). Both ADC inputs (INA+, INB+, INA-, and
INB-) can be driven either differentially or single-ended.
Match the impedance of INA+ and INA-, as well as
INB+ and INB-, and set the common-mode voltage to
midsupply (VDD / 2) for optimum performance.
Analog Inputs and Reference
Configurations
The full-scale range of the MAX1181 is determined by
the internally generated voltage difference between
REFP (VDD / 2 + VREFIN / 4) and REFN (VDD / 2 -
VREFIN / 4). The full-scale range for both on-chip ADCs is
adjustable through the REFIN pin, which is provided for
this purpose.
REFOUT, REFP, COM (VDD / 2) and REFN are internally
buffered low-impedance outputs.
The MAX1181 provides three modes of reference
operation:
Internal reference mode
Buffered external reference mode
Unbuffered external reference mode
In the internal reference mode, connect the internal ref-
erence output REFOUT to REFIN through a resistor
(e.g., 10k
Ω) or resistor divider, if an application
requires a reduced full-scale range.
Dual 10-Bit, 80Msps, 3V, Low-Power ADC
with Internal Reference and Parallel Outputs
10
______________________________________________________________________________________
Pin Description (continued)
PIN
NAME
FUNCTION
40
D5A
Three-State Digital Output, Bit 5, Channel A
41
D6A
Three-State Digital Output, Bit 6, Channel A
42
D7A
Three-State Digital Output, Bit 7, Channel A
43
D8A
Three-State Digital Output, Bit 8, Channel A
44
D9A
Three-State Digital Output, Bit 9 (MSB), Channel A
45
REFOUT
Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor
divider.
46
REFIN
Reference Input. VREFIN = 2 x (VREFP - VREFN). Bypass to GND with a > 1nF capacitor.
47
REFP
Positive Reference Input/Output. Conversion range is
±(VREFP - VREFN). Bypass to GND
with a > 0.1F capacitor.
48
REFN
Negative Reference Input/Output. Conversion range is
±(VREFP - VREFN). Bypass to GND
with a > 0.1F capacitor.
—
EP
Exposed Paddle. Connect to analog ground.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1181ECM-TD | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1181EVKIT | 功能描述:電源管理IC開(kāi)發(fā)工具 RoHS:否 制造商:Maxim Integrated 產(chǎn)品:Evaluation Kits 類型:Battery Management 工具用于評(píng)估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V |
| MAX1182ECM | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX1182ECM+D | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10-Bit 2Ch 65Msps High Speed ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1182ECM+TD | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10-Bit 2Ch 65Msps High Speed ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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