參數(shù)資料
型號: MAX1167BEEE+T
廠商: Maxim Integrated Products
文件頁數(shù): 2/30頁
文件大?。?/td> 0K
描述: IC ADC 16BIT 200KSPS 16-QSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
位數(shù): 16
采樣率(每秒): 200k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 667mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應商設備封裝: 16-QSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個單端,單極
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
10
______________________________________________________________________________________
Pin Description
PIN
MAX1167
MAX1168
NAME
FUNCTION
1
3
DOUT
Serial Data Output. Data changes state on SCLK’s falling edge in SPI/QSPI/MICROWIRE
mode and on SCLK’s rising edge in DSP mode (MAX1168 only). DOUT is high impedance
when CS is high.
2
4
SCLK
Serial Clock Input. SCLK drives the conversion process in external clock mode and clocks
data out.
3
5
DIN
Serial Data Input. Use DIN to communicate with the command/configuration/control
register. In SPI/QSPI/MICROWIRE mode, the rising edge of SCLK clocks in data at DIN. In
DSP mode, the falling edge of SCLK clocks in data at DIN.
46
EOC
End-of-Conversion Output. In internal clock mode, a logic low at EOC signals the end of a
conversion with the result available at DOUT. In external clock mode, EOC remains high.
5
7
AIN0
Analog Input 0
6
8
AIN1
Analog Input 1
7
9
AIN2
Analog Input 2
8
10
AIN3
Analog Input 3
9
15
REF
Reference Voltage Input/Output. VREF sets the analog voltage range. Bypass to AGND
with a 10F capacitor. Bypass with a 1F (min) capacitor when using internal reference.
10
16
REFCAP
Reference Bypass Capacitor Connection. Bypass to AGND with a 0.1F capacitor when
using internal reference. Internal reference and buffer shut down in external reference mode.
11
17
AGND
Analog Ground. Connect to pin 18 (MAX1168) or pin 12 (MAX1167).
12
18
AGND
Primary Analog Ground (Star Ground). Power return for AVDD.
13
19
AVDD
Analog Supply Voltage. Bypass to AGND with a 0.1F capacitor.
14
20
CS
Active-Low Chip-Select Input. Forcing CS high places the MAX1167/MAX1168 in shutdown
with a typical supply current of 0.6A. In SPI/QSPI/MICROWIRE mode, a high-to-low
transition on CS activates normal operating mode. In DSP mode, after the initial CS
transition from high to low, CS can remain low for the entire conversion process (see the
Operating Modes section).
15
21
DGND
Digital Ground
16
22
DVDD
Digital Supply Voltage. Bypass to DGND with a 0.1F capacitor.
1
DSPR
DSP Frame-Sync Receive Input. A frame-sync pulse received at DSPR initiates a
conversion. Connect to logic high when using SPI/QSPI/MICROWIRE mode.
2
DSEL
Data-Bit Transfer-Select Input. Logic low on DSEL places the device in 8-bit-wide data-
transfer mode. Logic high places the device in 16-bit-wide data-transfer mode. Do not
leave DSEL unconnected.
11
AIN4
Analog Input 4
12
AIN5
Analog Input 5
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