All WLP devices are 100% production tested at TA = +25°C. Specifications over t" />
參數(shù)資料
型號(hào): MAX11647EUA+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 18/22頁(yè)
文件大?。?/td> 0K
描述: IC ADC 10BIT I2C 94.4KSPS 8UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 50
位數(shù): 10
采樣率(每秒): 94.4k
數(shù)據(jù)接口: I²C,串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 362mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-uMAX
包裝: 管件
輸入數(shù)目和類型: 2 個(gè)單端,單極;2 個(gè)單端,雙極;1 個(gè)差分,單極;1 個(gè)差分,雙極
Note 1:
All WLP devices are 100% production tested at TA = +25°C. Specifications over temperature limits are guaranteed by
design and characterization.
Note 2:
For DC accuracy, the MAX11646 is tested at VDD = 5V and the MAX11647 is tested at VDD = 3V, with an external refer-
ence for both ADCs. All devices are configured for unipolar, single-ended inputs.
Note 3:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 4:
Offset nulled.
Note 5:
Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period.
Conversion time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6:
A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 7:
The absolute input voltage range for the analog inputs (AIN0/AIN1) is from GND to VDD.
Note 8:
When the internal reference is configured to be available at REF (SEL[2:1] = 11), decouple REF to GND with a 0.1F capaci-
tor and a 2k
Ω series resistor (see the Typical Operating Circuit).
Note 9:
ADC performance is limited by the converter’s noise floor, typically 300VP-P.
Note 10: Measured as follows for the MAX11647:
and for the MAX11646, where N is the number of bits:
Note 11: A master device must provide a data hold time for SDA (referred to VIL of SCL) to bridge the undefined region of SCL’s
falling edge (see Figure 1).
Note 12: The minimum value is specified at TA = +25°C.
Note 13: CB = total capacitance of one bus line in pF.
Note 14: fSCL must meet the minimum clock low time plus the rise/fall times.
VFS
VVFS
V
VREF
V
N
(.
)
( .
)
(.
55
45
2
55
×
45
.)
V
VV
V
FS
N
REF
(.
)
( .
)
(.
36
27
2
36
×
27
.)
V
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
_______________________________________________________________________________________
5
TIMING CHARACTERISTICS (Figure 1) (continued)
(VDD = 2.7V to 3.6V (MAX11647), VDD = 4.5V to 5.5V (MAX11646), VREF = 2.048V (MAX11647), VREF = 4.096V (MAX11646),
fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Tables 1–5 for programming
notation.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Rise Time of SCL Signal
(Current Source Enabled)
tRCL
Measured from 0.3VDD to 0.7VDD
20
80
ns
Rise Time of SCL Signal After
Acknowledge Bit
tRCL1
Measured from 0.3VDD to 0.7VDD
20
160
ns
Fall Time of SCL Signal
tFCL
Measured from 0.3VDD to 0.7VDD
20
80
ns
Rise Time of SDA Signal
tRDA
Measured from 0.3VDD to 0.7VDD
20
160
ns
Fall Time of SDA Signal
tFDA
Measured from 0.3VDD to 0.7VDD (Note 12)
20
160
ns
Setup Time for a STOP (P)
Condition
tSU:STO
160
ns
Capacitive Load for Each Bus
Line
CB
400
pF
Pulse Width of Spike
tSP
(Notes 11 and 14)
0
10
ns
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