- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17007 > MAX1132EVKIT (Maxim Integrated Products)KIT EVAL FOR MAX1132 PDF資料下載
參數(shù)資料
| 型號： | MAX1132EVKIT |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 19/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVAL FOR MAX1132 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±12 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 55mW @ 200kSPS |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | MAX1132，MAX1133 |
| 已供物品： | 板，CD |
The DIN input accepts Control Byte data which is
clocked in on each rising edge of SCLK. After
CS goes
low or after a conversion or calibration completes, the
first logic “1” clocked into DIN is interpreted as the
START bit, the MSB of the 8-bit Control Byte.
The SCLK input is the serial data transfer clock which
clocks data in and out of the MAX1132/MAX1133.
SCLK also drives the A/D conversion steps in external
clock mode (see Internal and External Clock Modes
section).
DOUT is the serial output of the conversion result.
DOUT is updated on the falling edge of SCLK. DOUT is
high-impedance when
CS is high.
CS must be low for the MAX1132/MAX1133 to accept a
Control Byte. The serial interface is disabled when
CS
is high.
User-Programmable Outputs
The MAX1132/MAX1133 have three user-programma-
ble outputs, P0, P1 and P2. The power-on default state
for the programmable outputs is zero. These are push-
pull CMOS outputs suitable for driving a multiplexer, a
PGA, or other signal preconditioning circuitry. The user-
programmable outputs are controlled by bits 0, 1, and
2 of the Control Byte (Table 2).
The user-programmable outputs are set to zero during
power-on reset (POR) or when
RST goes low. During
hardware or software shutdown P0, P1, and P2 are
unchanged and remain low-impedance.
Starting a Conversion
Start a conversion by clocking a Control Byte into the
device’s internal shift register. With
CS low, each rising
edge on SCLK clocks a bit from DIN into the
MAX1132/MAX1133’s internal shift register. After
CS
goes low or after a conversion or calibration completes,
the first arriving logic “1” is defined as the start bit of
the Control Byte. Until this first start bit arrives, any
number of logic “0” bits can be clocked into DIN with
no effect. If at any time during acquisition or conversion,
CS is brought high and then low again, the part is
placed into a state where it can recognize a new start
bit. If a new start bit occurs before the current conver-
sion is complete, the conversion is aborted and a new
acquisition is initiated.
Internal and External Clock Modes
The MAX1132/MAX1133 may use either the external
serial clock or the internal clock to perform the succes-
sive-approximation conversion. In both clock modes,
the external clock shifts data in and out of the
MAX1132/MAX1133. Bit 5 (INT/
EXT) of the Control Byte
programs the clock mode.
External Clock
In external clock mode, the external clock not only
shifts data in and out, but it also drives the ADC con-
version steps. In short acquisition mode, SSTRB pulses
high for one clock period after the seventh falling edge
of SCLK following the start bit. The MSB of the conver-
sion is available at DOUT on the eighth falling edge of
SCLK (Figure 2).
In long acquisition mode, when using external clock,
SSTRB pulses high for one clock period after the fif-
teenth falling edge of SCLK following the start bit. The
MSB of the conversion is available at DOUT on the six-
teenth falling edge of SCLK (Figure 3).
In external clock mode, SSTRB is high-impedance
when
CS is high. In external clock mode, CS is normally
held low during the entire conversion. If
CS goes high
during the conversion, SCLK is ignored until
CS goes
low. This allows external clock mode to be used with 8-
bit bytes.
Internal Clock
In internal clock mode, the MAX1132/MAX1133 gener-
ates its own conversion clock. This frees the micro-
processor from the burden of running the SAR conver-
sion clock, and allows the conversion results to be read
back at the processor’s convenience, at any clock rate
up to 8MHz.
SSTRB goes low at the start of the conversion and goes
high when the conversion is complete. SSTRB will be
MAX1132/MAX1133
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
_______________________________________________________________________________________
9
S1 = BIPOLAR/UNIPOLAR
S2, S3 = T/H SWITCH
S3
S2
AIN
S1
R1
2.5k
R3
R2
VOLTAGE
REFERENCE
T/H OUT
HOLD
TRACK
BIPOLAR
UNIPOLAR
R2 = 7.6k (MAX1132)
OR 2.5k (MAX1133)
R3 = 3.9k (MAX1132)
OR INFINITY (MAX1133)
CHOLD
30pF
Figure 1. Equivalent Input Circuit
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HCM10DRTI-S13 | CONN EDGECARD 20POS .156 EXTEND |
| AC2626K4 | PROBE TEMP 4" GENERAL PURP |
| HBM10DRTI-S13 | CONN EDGECARD 20POS .156 EXTEND |
| 0210490252 | CABLE JUMPER 1.25MM .254M 18POS |
| ADZS-AUDIO-EX3 | BOARD EXTENDER AUDIO EI3 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1132EVSYS | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Evaluation System for the MAX1132/MAX1133 |
| MAX1132-MAX1133 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:16-Bit ADC, 200ksps, 5V Single-Supply with Reference |
| MAX1133 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:16-Bit ADC, 200ksps, 5V Single-Supply with Reference |
| MAX11330 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:3Msps, 12-/10-Bit, 8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access |
| MAX11330ATJ | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:3Msps, 12-/10-Bit, 8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。