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參數資料
| 型號： | MAX1126 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs |
| 中文描述： | 四路、12位、40Msps、1.8V ADC，串行LVDS輸出 |
| 文件頁數： | 14/25頁 |
| 文件大?。?/td> | 790K |
| 代理商： | MAX1126 |
M
Quad, 12-Bit, 40Msps, 1.8V ADC with
S erial LV DS Outputs
14
______________________________________________________________________________________
Typic al Operating Charac teristic s (c ontinued)
(AV
DD
= 1.8V, OV
DD
= 1.8V, CV
DD
= 1.8V, GND = 0, external V
REFIO
= 1.24V,
INTREF
= AV
DD
, differential input at -0.5dBFS,
f
CLK
= 40MHz (50% duty cycle), DT = low, C
LOAD
= 10pF, T
A
= +25°C, unless otherwise noted.)
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
V
R
2.0
1.9
1.8
1.236
1.237
1.238
1.239
1.235
1.7
2.1
M
AV
DD
= OV
DD
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
TEMPERATURE (
°
C)
V
R
60
35
10
-15
1.23
1.24
1.25
1.26
1.22
-40
85
M
AV
DD
= OV
DD
INTERNAL REFERENCE VOLTAGE
vs. REFERENCE LOAD CURRENT
I
REFIO
(
μ
A)
V
R
300
200
-300 -200 -100
0
100
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.00
-400
400
M
NEGATIVE CURRENT
FLOWS INTOREFIO
PIN
NAME
FUNCTION
1, 4, 7, 11,
14, 17, 22,
24, 65, 68
GND
Ground. Connect all GND pins to the same potential.
2
3
5
6
IN0P
IN0N
IN1P
IN1N
Channel 0 Positive Analog Input
Channel 0 Negative Analog Input
Channel 1 Positive Analog Input
Channel 1 Negative Analog Input
8, 9, 10, 18,
20, 25, 26,
27, 58–62
AV
DD
Analog Power Input. Connect AV
DD
to a 1.7V to 1.9V power supply. Bypass each AV
DD
to GND with
a 0.1μF capacitor as close to the device as possible. Bypass the AV
DD
power plane to the GND
ground plane with a bulk
≥
2.2μF capacitor as close to the device as possible. Connect all AV
DD
pins
to the same potential.
12
13
15
16
19
IN2P
IN2N
IN3P
IN3N
I.C.
Channel 2 Positive Analog Input
Channel 2 Negative Analog Input
Channel 3 Positive Analog Input
Channel 3 Negative Analog Input
Internally Connected. Do not connect.
21
CV
DD
Clock Power Input. Connect CV
DD
to a 1.7V to 3.6V supply. Bypass CV
DD
to GND with a 0.1μF
capacitor in parallel with a
≥
2.2μF capacitor. Install the bypass capacitors as close to the device as
possible.
23
CLK
Single-Ended CMOS Clock Input
28
DT
Double Termination Select Input. Drive DT high to select the internal 100
termination between the
differential output pairs. Drive DT low to select no internal output termination.
Pin Desc ription
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