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參數(shù)資料
| 型號： | MAX11101EWC+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 8/19頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT SRL 200KSPS 12WLP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.3W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 12-WFBGA，WLCSP |
| 供應商設備封裝： | 12-WLP |
| 包裝： | 標準包裝 |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
| 其它名稱： | MAX11101EWC+TDKR |
Maxim Integrated Products 16
MAX11101
14-Bit, +5V, 200ksps ADC with 10A Shutdown
Table 1. Detailed SSPCON Register Contents
Table 2. Detailed SSPSTAT Register Contents
Figure 12b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 =0001)
CONTROL BIT
MAX11101
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL
BIT 7
X
Write Collision Detection Bit
SSPOV
BIT 6
X
Receive Overflow Detect Bit
SSPEN
BIT 5
1
Synchronous Serial-Port Enable Bit:
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins.
CKP
BIT 4
0
Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
SSPM3
BIT 3
0
Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and selects fCLK = fOSC/16
SSPM2
BIT 2
0
SSPM1
BIT 1
0
SSPM0
BIT 0
1
CONTROL BIT
MAX11101
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPSTAT)
SMP
BIT 7
0
SPI Data Input Sample Phase. Input data is sampled at the middle of the data output time.
CKE
BIT 6
1
SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock.
D/A
BIT 5
X
Data Address Bit
P
BIT 4
X
STOP Bit
S
BIT 3
X
START Bit
R/W
BIT 2
X
Read/Write Bit Information
UA
BIT 1
X
Update Address
BF
BIT 0
X
Buffer Full Status Bit
DOUT*
CS
SCLK
1ST BYTE READ
2ND BYTE READ
*WHEN CS IS HIGH, DOUT = HIGH-Z
MSB
HIGH-Z
3RD BYTE READ
LSB
S1
S0
D5
D4
D3
D2
D1
D0
24
20
16
12
D13
D12
D11
D10
D9
D8
D7
D6
0
00
000
00
D5
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