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參數(shù)資料
| 型號(hào)： | MAX11101EUB+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT SRL 200KSPS 10UMAX |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 444mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-uMAX |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極 |
| 其它名稱： | MAX11101EUB+TDKR |
Maxim Integrated Products 10
MAX11101
14-Bit, +5V, 200ksps ADC with 10A Shutdown
During the acquisition, the analog input (AIN) charges
capacitor CDAC. The acquisition interval ends on the
falling edge of the sixth clock cycle (Figure 6). At this
instant, the T/H switches open. The retained charge on
CDAC represents a sample of the input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to zero within the limits of
14-bit resolution. At the end of the conversion, force CS
high and then low to reset the input side of the CDAC
switches back to AIN, and charge CDAC to the input
signal again.
The time required for the T/H to acquire an input signal is
a function of how quickly its input capacitance is charged.
If the input signal’s source impedance is high, the acqui-
sition time lengthens and more time must be allowed
between conversions. The acquisition time (tACQ) is the
maximum time the device takes to acquire the signal. Use
the following formula to calculate acquisition time:
tACQ = 11(RS + RIN) x 35pF
where RIN = 800I, RS = the input signal’s source
impedance, and tACQ is never less than 1.1Fs. A source
impedance less than 1kI does not significantly affect the
ADC’s performance.
To improve the input signal bandwidth under AC condi-
tions, drive AIN with a wideband buffer (> 4MHz) that
can drive the ADC’s input capacitance and settle quickly.
Input Bandwidth
The ADC’s input tracking circuitry has a 4MHz small-
signal bandwidth, so it is possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by using
undersampling techniques. To avoid aliasing of unwant-
ed high-frequency signals into the frequency band of
interest, use anti-alias filtering.
Analog Input Protection
Internal protection diodes, which clamp the analog input to
AVDD and/or AGND, allow the input to swing from VAGND -
0.3V to VAVDD + 0.3V, without damaging the device.
If the analog input exceeds 300mV beyond the supplies,
limit the input current to 10mA.
Digital Interface
Initialization After Power-Up
and Starting a Conversion
The digital interface consists of two inputs, SCLK and
CS, and one output, DOUT. A logic-high on CS places
the MAX11101 in shutdown (autoshutdown) and places
DOUT in a high-impedance state. A logic-low on CS
places the MAX11101 in the fully powered mode.
To start a conversion, pull CS low. A falling edge on CS
initiates an acquisition. SCLK drives the A/D conversion
and shifts out the conversion results (MSB first) at DOUT.
Timing and Control
Conversion-start and data-read operations are con-
trolled by the CS and SCLK digital inputs (Figure 6
and Figure 7). Ensure that the duty cycle on SCLK is
between 40% and 60% at 4.8MHz (the maximum clock
frequency). For lower clock frequencies, ensure that
the minimum high and low times are at least 65ns.
Conversions with SCLK rates less than 100kHz may
result in reduced accuracy due to leakage.
Note: Coupling between SCLK and the analog inputs
(AIN and REF) may result in an offset. Variations in
frequency, duty cycle, or other aspects of the clock
signal’s shape result in changing offset.
Figure 4. Typical Operating Circuit
Figure 5. Equivalent Input Circuit
SCLK
DOUT
AGND
DGND
AIN
REF
AVDD
DVDD
DOUT
SCLK
CS
AIN
VREF
+5V
4.7F
0.1F
GND
MAX11101
CS
CDAC 32pF
RIN
800
HOLD
CSWITCH
3pF
AIN
REF
GND
ZERO
CAPACITIVE DAC
AUTOZERO
RAIL
TRACK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX11101EWC | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:14-Bit, +5V, 200ksps ADC with 10μA Shutdown |
| MAX11101EWC+ | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:14-Bit, 5V, 200ksps ADC with 10??A Shutdown |
| MAX11101EWC+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14-Bit 5V 200ksps w/10uA Shutdown RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX11102 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs |
| MAX11102_11 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs 2.2V to 3.6V Supply Voltage |
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