參數(shù)資料
型號: MAX11059ECB+
廠商: Maxim Integrated Products
文件頁數(shù): 6/25頁
文件大?。?/td> 0K
描述: IC ADC 14BIT PAR 250KSPS 64TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
位數(shù): 14
采樣率(每秒): 250k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 8
功率耗散(最大): 3.48W
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-TQFP-EP(10x10)
包裝: 管件
輸入數(shù)目和類型: 8 個單端,單極
MAX11047–MAX11049/MAX11057–MAX11059
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
14
______________________________________________________________________________________
Detailed Description
The MAX11047/MAX11048/MAX11049 and MAX11057/
MAX11058/MAX11059 are fast, low-power ADCs that
combine 4, 6, or 8 independent ADC channels in a sin-
gle IC. Each channel includes simultaneously sampling
independent T/H circuitry that preserves relative phase
information between inputs making the devices ideal for
motor control and power monitoring. The devices are
available with a 0 to 5V input range that features
±20mA overrange, fault-tolerant inputs. The devices
operate with a single 4.75V to 5.25V supply. A separate
2.7V to 5.25V supply for digital circuitry makes the
devices compatible with low-voltage processors.
The devices perform conversions for all channels in paral-
lel by activating independent ADCs. Results are available
through a high-speed, 20MHz, parallel data bus after a
conversion time of 3s following the end of a sample. The
data bus is bidirectional and allows for easy program-
ming of the configuration register. The devices feature a
reference buffer, which is driven by an internal bandgap
reference circuit (VREFIO = 4.096V). Drive REFIO with an
external reference or bypass with a 0.1F capacitor to
ground when using the internal reference.
Analog Inputs
Track and Hold (T/H)
To preserve phase information across all channels,
each input includes a dedicated T/H circuitry. The input
tracking circuitry provides a 4MHz small-signal band-
width, enabling the device to digitize high-speed tran-
sient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Use anti-alias filtering
to avoid high-frequency signals being aliased into the
frequency band of interest.
Pin Description (continued)
PIN
MAX11057
(TQFP-EP)
MAX11058
(TQFP-EP)
MAX11059
(TQFP-EP)
NAME
FUNCTION
41
REFIO
External Reference Input/Internal Reference Output. Place a 0.1F capacitor
from REFIO to AGND.
42
39
37
CH2
Channel 2 Analog Input
44
42
39
CH3
Channel 3 Analog Input
44
42
CH4
Channel 4 Analog Input
47
44
CH5
Channel 5 Analog Input
47
CH6
Channel 6 Analog Input
50
CH7
Channel 7 Analog Input
61
WR
Active-Low Write Input. Drive WR low to write to the ADC. Configuration
registers are loaded on the rising edge of WR.
62
CS
Active-Low Chip-Select Input. Drive CS low when reading from or writing to
the ADC.
63
RD
Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge
of RD advances the channel output on the data bus.
64
DB13
14-Bit Parallel Data Bus Digital Out Bit 13
——
EP
Exposed Pad. Internally connected to AGND. Connect to a large ground
plane to maximize thermal performance. Not intended as an electrical
connection point.
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