參數(shù)資料
型號(hào): MAX11059ECB+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 21/25頁(yè)
文件大小: 0K
描述: IC ADC 14BIT PAR 250KSPS 64TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
位數(shù): 14
采樣率(每秒): 250k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 8
功率耗散(最大): 3.48W
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 64-TQFP-EP(10x10)
包裝: 管件
輸入數(shù)目和類型: 8 個(gè)單端,單極
MAX11047–MAX11049/MAX11057–MAX11059
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
_______________________________________________________________________________________
5
Typical Operating Characteristics
(VAVDD = 5V, VDVDD = 3.3V, TA = +25°C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.)
INTEGRAL NONLINEARITY (INL)
vs. CODE FOR MAX1104_
MAX11047
toc01
OUTPUT CODE (DECIMAL)
INL
(LSBs)
57344
49152
32768
40960
16384
24576
8192
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0
65536
VAVDD = 5.0V
VDVDD = 3.3V
fSAMPLE = 250ksps
TA = +25°C
VRDC = 4.096V
DIFFERENTIAL NONLINEARITY (DNL)
vs. CODE FOR MAX1104_
MAX11047
toc02
OUTPUT CODE (DECIMAL)
DNL
(LSBs)
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
VAVDD = 5.0V
VDVDD = 3.3V
fSAMPLE = 250ksps
TA = +25°C
VRDC = 4.096V
57344
49152
32768
40960
16384
24576
8192
0
65536
ELECTRICAL CHARACTERISTICS (continued)
VAVDD = 4.75V to 5.25V, VDVDD = +2.7V to 5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33F,
CREFIO = 0.1F, CAVDD = 4 x 0.1F || 10F, CDVDD = 3 x 0.1F || 10F; all digital inputs at DVDD or DGND, unless otherwise noted.
TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
Note 1: See the
Definitions section at the end of the data sheet.
Note 2: Tested with alternating channels modulated at full scale and ground.
Note 3: See the
Input Range and Protection section.
Note 4: CLOAD= 30pF on DB0–DB15 and EOC. Inputs (CH0–CH7) alternate between full scale and zero scale. fCONV = 250ksps. All
data is read out.
Note 5: Defined as the change in positive full scale caused by a ±2% variation in the nominal supply voltage.
Note 6: It is recommended that RD, WR, and CS are kept high for the quiet time (tQ) and conversion time (tCON).
Note 7: Guaranteed by design.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONVST Rise to
EOC Rise
t0
65
140
ns
EOC Fall to CONVST Fall
t1
CONVST mode B0 = 0 only (Note 7)
0
ns
CONVST Low Time
t2
CONVST mode B0 = 1 only
20
ns
CS Fall to WR Fall
t3
0
ns
WR Low Time
t4
20
ns
CS Rise to WR Rise
t5
0
ns
Input Data Setup Time
t6
10
ns
Input Data Hold Time
t7
0
ns
CS Fall to RD Fall
t8
0
ns
RD Low Time
t9
30
ns
RD Rise to CS Rise
t10
0
ns
RD High Time
t11
10
ns
RD Fall to Data Valid
t12
35
ns
RD Rise to Data Hold Time
t13
(Note 7)
5
ns
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