參數(shù)資料
型號(hào)： MAX11044ETN+T
廠商： Maxim Integrated Products
文件頁數(shù)： 6/28頁
文件大?。?/td> 0K
描述： ADC 16BIT SAMPLING 4CH 56-TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 16
采樣率（每秒）： 250k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 3.81W
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 56-TQFN-EP（8x8）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個(gè)單端，雙極
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
14
Maxim Integrated
MAX11044/MAX11044B/MAX11045/MAX11045B/
MAX11046/MAX11046B/MAX11054/MAX11055/MAX11056
Pin Description (continued)
PIN
MAX11054
(TQFP-EP)
MAX11055
(TQFP-EP)
MAX11056
(TQFP-EP)
NAME
FUNCTION
1
DB12
14-Bit Parallel Data Bus Digital Output Bit 12
2
DB11
14-Bit Parallel Data Bus Digital Output Bit 11
3
DB10
14-Bit Parallel Data Bus Digital Output Bit 10
4
DB9
14-Bit Parallel Data Bus Digital Output Bit 9
5
DB8
14-Bit Parallel Data Bus Digital Output Bit 8
6
DB7
14-Bit Parallel Data Bus Digital Output Bit 7
7
DB6
14-Bit Parallel Data Bus Digital Output Bit 6
8, 22, 59
DGND
Digital Ground
9, 21, 60
DVDD
Digital Supply. Bypass to DGND with a 0.1μF capacitor
at each DVDD input.
10
DB5
14-Bit Parallel Data Bus Digital Output Bit 5
11
DB4
14-Bit Parallel Data Bus Digital Output Bit 4
12
DB3
14-Bit Parallel Data Bus Digital Output Bit 3
13
DB2
14-Bit Parallel Data Bus Digital Output Bit 2
14
DB1/CR3
14-Bit Parallel Data Bus Digital Output Bit 1/
Configuration Register Input Bit 3
15
DB0/CR2
14-Bit Parallel Data Bus Digital Output Bit 0/
Configuration Register Input Bit 2
16
CR1
Configuration Register Input Bit 1
17
CR0
Configuration Register Input Bit 0
18
EOC
Active-Low End-of-Conversion Output. EOC goes low
when conversion is completed. EOC goes high when a
conversion is initiated.
19
CONVST
Convert Start Input. Rising edge of CONVST ends
sample and starts a conversion on the captured sample.
The ADC is in acquisition mode when CONVST is low
and CONVST mode = 0.
20
SHDN
Shutdown Input. If SHDN is held high, the entire device
will enter and stay in a low-current state. Contents of
the configuration register are not lost when in the
shutdown mode.
23, 28, 32, 38,
43, 49, 53, 58
23, 28, 32, 38,
43, 49, 53, 58
23, 28, 32, 38,
43, 49, 53, 58
AGNDS
Signal Ground. Connect all AGND and AGNDS inputs
together on PCB.
24, 29, 35, 46,
52, 57
24, 29, 35, 46,
52, 57
24, 29, 35, 46,
52, 57
AVDD
Analog Supply Input. Bypass AVDD to AGND with a
0.1μF capacitor at each AVDD input.
25, 30, 36, 45,
51, 56
25, 30, 36, 45,
51, 56
25, 30, 36, 45,
51, 56
AGND
Analog Ground. Connect all AGND inputs together.
26, 55
RDC_SENSE
Reference Buffer Sense Feedback. Connect to RDC plane.
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