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參數(shù)資料
| 型號： | MAX11044ETN+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | ADC 16BIT SAMPLING 4CH 56-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 功率耗散（最大）： | 3.81W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 56-TQFN-EP（8x8） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個(gè)單端，雙極 |
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4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
18
Maxim Integrated
MAX11044/MAX11044B/MAX11045/MAX11045B/
MAX11046/MAX11046B/MAX11054/MAX11055/MAX11056
Starting a Conversion
CONVST initiates conversions. The MAX11044/MAX11044B
MAX11045/MAX11045B/MAX11046/MAX11046B and
MAX11054/MAX11055/MAX11056 provide two acquisition
modes set through the configuration register. Allow a quiet
time (tQ) of 500ns prior to the start of conversion to avoid
any noise interference during readout or write operations
from corrupting a sample.
In default mode (CR0 = 0), drive CONVST low to place the
MAX11044/MAX11044B/MAX11045/MAX11045B/
MAX11046/MAX11046B and MAX11054/MAX11055/
MAX11056 into acquisition mode. All the input switches
are closed and the internal T/H circuits track the respective
input voltage. Keep the CONVST signal low for at least 1μs
(tACQ) to enable proper settling of the sampled voltages.
On the rising edge of CONVST, the switches are opened
and the MAX11044/MAX11044B/MAX11045/MAX11045B/
MAX11046/MAX11046B and MAX11054/MAX11055/
MAX11056 begin the conversion on all the samples in par-
allel. EOC remains high until the conversion is completed.
In the second mode (CR0 = 1), the MAX11044/
MAX11044B/MAX11045/MAX11045B/MAX11046/
MAX11046B and MAX11054/MAX11055/MAX11056
enter acquisition mode as soon as the previous conver-
sion is completed. CONVST rising edge initiates the
next sample and conversion sequence. CONVST needs
to be low for at least 20ns to be valid.
Provide adequate time for acquisition and the requisite
quiet time in both modes to achieve accurate sampling
and maximum performance of the MAX11044/
MAX11044B/MAX11045/MAX11045B/MAX11046/MAX1
1046B and MAX11054/MAX11055/MAX11056.
Reading Conversion Results
The CS and RD are active-low, digital inputs that con-
trol the readout through the 16-/14-bit, parallel, 20MHz
data bus (D0–D15/D13). After EOC transitions low, read
the conversion data by driving CS and RD low. Each
low period of RD presents the next channel’s result.
When CS or RD are high, the data bus is high imped-
ance. CS may be driven high between individual chan-
nel readouts or left low during the entire 8-channel
readout.
Reference
Internal Reference
The MAX11044/MAX11044B/MAX11045/MAX11045B/
MAX11046/MAX11046B and MAX11054/MAX11055/
MAX11056 feature a precision, low-drift, internal
bandgap reference. Bypass REFIO with a 0.1μF capaci-
tor to AGND to reduce noise. The REFIO output voltage
may be used as a reference for other circuits. The output
impedance of REFIO is 10k
Ω. Drive only high impedance
circuits or buffer externally when using REFIO to drive
external circuitry.
External Reference
Set the configuration register to disable the internal ref-
erence and drive REFIO with a high-quality external ref-
erence. To avoid signal degradation, ensure that the
integrated reference noise applied to REFIO is less
than 10μV in the bandwidth of up to 50kHz.
Sn
Sn + 1
t8
t12
t13
t9
t10
t11
RD
(USER SUPPLIED)
CS
(USER SUPPLIED)
DB0–DB15/DB13
Figure 5. Readout Timing Requirements
CONFIGURATION
REGISTER
t6
t3
t4
t5
t7
WR
(USER SUPPLIED)
CS
(USER SUPPLIED)
CR0–CR3
(USER SUPPLIED)
Figure 4. Programming Configuration-Register Timing
Requirements
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