參數(shù)資料
型號(hào)： MAX109EHF-D
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi)： ADC
英文描述： 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
中文描述： 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, BGA256
封裝： 27 X 27 MM, 1.27 MM PITCH, SBGA-256
文件頁(yè)數(shù)： 24/29頁(yè)
文件大?。?/td> 451K
代理商： MAX109EHF-D
M
reset signal to match the latency of the converted ana-
log data through the ADC. In this way, when reset data
arrives at the RSTOUTP/RSTOUTN LVDS output it will
be time-aligned with the analog data present in data
ports PortA, PortB, PortC, and PortD at the time the
reset input was deasserted.
Demultiplexer Clock Generator
The demultiplexer clock generator creates the clocks
required for the different modes of demultiplexer opera-
tion. DDR and QDR control the demultiplexed mode
selection, as described in Table 2. The timing diagrams
in Figures 6, 7, and 8 show the output timing and data
alignment for SDR, DDR, and QDR modes, respective-
ly. The phase relationship between the sampling clock
at the CLKP/CLKN inputs and the DCO clock at the
DCOP/DCON outputs is random at device power-up.
Reset all MAX109 devices to a known DCO phase after
initial power-up for applications such as interleaving,
where two or more MAX109 devices are used to
achieve higher effective sampling rates. This synchro-
nization is necessary to set the order of output samples
between the devices. Resetting the converters accom-
plishes this synchronization. The reset signal is used to
force the internal counter in the demultiplexer clock-
generator block to a known phase state.
Reset Output
Finally, the reset signal is presented in true LVDS for-
mat to the last block of the reset signal path. RSTOUT
outputs the time-aligned reset signal, used for resetting
additional external demultiplexers in applications that
need further output data-rate reduction. Many demulti-
plexer devices require their reset signal to be asserted
for several clock cycles while they are clocked. To
accomplish this, the MAX109 DCO clock will continue
to toggle while RSTOUT is asserted. When a single
MAX109 device is used, no synchronizing reset is
required because the order of the samples in the out-
put ports remains unchanged, regardless of the phase
of the DCO clock. In all modes, RSTOUT is delayed by
7.5 clock cycles, starting with the first rising edge of
CLKP following the falling edge of the RSTINP signal.
With the next reset cycle PortD data shows the expect-
ed and proper data on the output, while the remaining
three ports (PortA, PortB, and PortC) keep their previ-
ous data, which may or may not be swallowed,
depending on the power-up state of the demultiplexer
clock generator. With the next cycle, the right data is
presented for all four ports in the proper order. The
aforementioned reset output and data-reset operation
is valid for SDR, DDR, and QDR modes.
Die Temperature Measurement
The die temperature of the MAX109 can be determined
by monitoring the voltage V
TEMPMON
between the
TEMPMON output and GNDI. The corresponding volt-
age is proportional to the actual die temperature of the
converter and can be calculated as follows:
T
DIE
(°C) = [(V
TEMPMON
- V
GNDI
)
×
1303.5] - 371
The MAX109 exhibits a typical TEMPMON voltage of
0.35V, resulting in an overall die temperature of +90°C.
The converter’s die temperature can be lowered con-
siderably by cooling the MAX109 with a properly sized
heatsink. Adding airflow across the part with a small fan
can further lower the die temperature, making the sys-
tem more thermally manageable and stable.
Thermal Management
Depending on the application environment for the
SBGA-packaged MAX109, the user can apply an exter-
nal heatsink with integrated fan to the package after
board assembly. Existing open-tooled heatsinks with
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier
and 1:4 Demultiplexed LVDS Outputs
24
______________________________________________________________________________________
RSTINP
50%
50%
CLKP
CLKN
RSTINN
50%
t
SU
t
HD
Figure 15. Timing Relationship between Sampling Clock and
Reset Input
500
500
100k
RSTINP
RSTINN
SIMPLIFIED DIAGRAM
(INPUT ESD PROTECTION
NOT SHOWN)
GNDD
V
CC
O
V
CC
O
Figure 14. Reset Circuitry—Input Structure
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