參數(shù)資料
型號(hào)： MAX109EHF-D
廠(chǎng)商： MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi)： ADC
英文描述： 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
中文描述： 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, BGA256
封裝： 27 X 27 MM, 1.27 MM PITCH, SBGA-256
文件頁(yè)數(shù)： 23/29頁(yè)
文件大小： 451K
代理商： MAX109EHF-D
M
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier
and 1:4 Demultiplexed LVDS Outputs
______________________________________________________________________________________
23
50
reverse-terminated to GNDI. The dynamic perfor-
mance of the data converter is essentially unaffected
by clock-drive power levels from -10dBm to +10dBm.
The MAX109 dynamic performance specifications are
determined by a single-ended clock drive of 10dBm.
To avoid saturation of the input amplifier stage, limit the
clock power level to a maximum of 15dBm.
Differential Clock Inputs (Sine-Wave Drive)
The advantages of differential clock drive (Figure 13b,
Table 6) can be obtained by using an appropriate
balun transformer to convert single-ended sine-wave
sources into differential drives. The precision on-chip,
laser-trimmed 50
clock-termination resistors ensure
excellent amplitude matching. See the Single-Ended
Clock Inputs (Sine-Wave Drive) section for proper input
amplitude requirements.
Single-Ended Clock Inputs (ECL Drive)
Configure the MAX109 for single-ended ECL clock
drive by connecting the clock inputs as shown in Figure
13c and Table 6. A well-bypassed V
BB
supply (-1.3V) is
essential to avoid coupling noise into the undriven
clock input, which would degrade dynamic perfor-
mance.
Differential Clock Inputs (ECL Drive)
Drive the MAX109 from a standard differential ECL
clock source (Figure 13d, Table 6) by setting the clock
termination voltage at CLKCOM to -2V. Bypass the
clock termination return (CLKCOM) as close to the ADC
as possible with a 0.01μF capacitor connected to
GNDI.
Demultiplexer Reset Operation
The MAX109 features an internal 1:4 demultiplexer that
reduces the data rate of the output digital data to one-
quarter the sample clock rate. A reset for the demulti-
plexer is necessary when interleaving multiple MAX109
converters and/or synchronizing external demultiplex-
ers. The simplified block diagram of Figure 1 shows
that the demultiplexer reset signal path consists of four
main circuit blocks. From input to output, they are the
reset input dual latch, the reset pipeline, the demulti-
plexer clock generator, and the reset output. The sig-
nals associated with the demultiplexer-reset operation
and the control of this section are listed in Table 7.
Reset Input Dual Latch
The reset input dual-latch circuit block accepts LVDS
reset inputs. For applications that do not require a syn-
chronizing reset, the reset inputs may be left open.
Figure 14 shows a simplified schematic of the reset
input structure. To latch the reset input data properly,
the setup time (t
SU
) and the data-hold time (t
HD
) must
be met with respect to the rising edge of the sample
clock. The timing diagram of Figure 15 shows the tim-
ing relationship of the reset input and sampling clock.
Reset Pipeline
The next section in the reset signal path is the reset
pipeline. This block adds clock cycles of latency to the
CLKP
CLKN = 0V
+0.5V
-0.5V
NOTE: CLKCOM = 0V
t
Figure 13a. Single-Ended Clock Input—Sine-Wave Drive
CLKP
CLKN
+0.5V
-0.5V
NOTE: CLKCOM = 0V
t
Figure 13b. Differential Clock Input—Sine-Wave Drive
CLKP
-0.8V
-1.8V
NOTE: CLKCOM = -2V
t
CLKN = -1.3V
Figure 13c. Single-Ended Clock Input—ECL Drive
CLKP
CLKN
-0.8V
-1.8V
NOTE: CLKCOM = -2V
t
Figure 13d. Differential Clock Input—ECL Drive
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