參數(shù)資料
型號(hào)： MAX1089ETA+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 14/15頁(yè)
文件大小： 0K
描述： IC ADC 10BIT 150KSPS 8-TDFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 10
采樣率（每秒）： 150k
數(shù)據(jù)接口： MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 740µW
電壓電源： 單電源
工作溫度： -40°C ~ 80°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 8-WDFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 8-TDFN-EP（3x3）
包裝： 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類(lèi)型： 1 個(gè)差分，單極；1 個(gè)差分，雙極
產(chǎn)品目錄頁(yè)面： 1395 (CN2011-ZH PDF)
其它名稱(chēng)： MAX1089ETA+TDKR
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23 and TDFN
8
_______________________________________________________________________________________
where RIN = 1.5k
Ω, RS is the source impedance of the
input signal, and tPWR = 1s is the power-up time of the
device.
Note: tACQ is never less than 1.4s and any source
impedance below 300
Ω does not significantly affect the
ADC‘s AC performance. A high impedance source can
be accommodated either by lengthening tACQ or by
placing a 1F capacitor between the positive and neg-
ative analog inputs.
Selecting AIN1 or AIN2
(MAX1086/MAX1087)
Select between the MAX1086/MAX1087’s two positive
input channels using the CNVST pin. If AIN1 is desired
(Figure 5a), drive CNVST high to power-up the ADC
and place the T/H in track mode with AIN1 connected
to the positive input capacitor. Hold CNVST high for
tACQ to fully acquire the signal. Drive CNVST low to
place the T/H in hold mode. The ADC will then perform
a conversion and shutdown automatically. The MSB is
available at DOUT after 3.7s. Data can then be
clocked out using SCLK. Be sure to clock out all 12 bits
of data (the 10-bit result plus two sub-bits) before dri-
ving CNVST high for the next conversion. If all 12 bits of
data are not clocked out before CNVST is driven high,
AIN2 will be selected for the next conversion.
If AIN2 is desired (Figure 5b), drive CNVST high for at
least 30ns. Next, drive it low for at least 30ns, and then
high again. This will power-up the ADC and place the
T/H in track mode with AIN2 connected to the positive
input capacitor. Now hold CNVST high for tACQ to fully
acquire the signal. Drive CNVST low to place the T/H in
hold mode. The ADC will then perform a conversion
and shutdown automatically. The MSB is available at
DOUT after 3.7s. Data can then be clocked out using
SCLK. If all 12 bits of data are not clocked out before
CNVST is driven high, AIN2 will be selected for the next
conversion.
Selecting Unipolar or Bipolar Conversions
(MAX1088/MAX1089)
Initiate true-differential conversions with the
MAX1088/MAX1089’s unipolar and bipolar modes,
using the CNVST pin. AIN+ and AIN- are sampled at
the falling edge of CNVST. In unipolar mode, AIN+ can
exceed AIN- by up to VREF. The output format is
straight binary. In bipolar mode, either input can
exceed the other by up to VREF/2. The output format is
two’s complement.
Note: In both modes, AIN+ and AIN- must not exceed
VDD by more than 50mV or be lower than GND by more
than 50mV.
If unipolar mode is desired (Figure 5a), drive CNVST
high to power-up the ADC and place the T/H in track
mode with AIN+ and AIN- connected to the input
capacitors. Hold CNVST high for tACQ to fully acquire
the signal. Drive CNVST low to place the T/H in hold
mode. The ADC will then perform a conversion and
shutdown automatically. The MSB is available at DOUT
after 3.7s. Data can then be clocked out using SCLK.
Be sure to clock out all 12 bits (the 10-bit result plus
two sub-bits) of data before driving CNVST high for the
next conversion. If all 12 bits of data are not clocked
out before CNVST is driven high, bipolar mode will be
selected for the next conversion.
If bipolar mode is desired (Figure 5b), drive CNVST
high for at least 30ns. Next, drive it low for at least 30ns
and then high again. This will place the T/H in track
mode with AIN+ and AIN- connected to the input
capacitors. Now hold CNVST high for tACQ to fully
acquire the signal. Drive CNVST low to place the T/H in
hold mode. The ADC will then perform a conversion
and shutdown automatically. The MSB is available at
DOUT after 3.7s. Data can then be clocked out using
SCLK. If all 12 bits of data are not clocked out before
CNVST is driven high, bipolar mode will be selected for
the next conversion.
Input Bandwidth
The ADCs input tracking circuitry has a 1MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
RIN+
+
-
HOLD
RIN-
CIN+
REF
GND
DAC
CIN-
TRACK
VDD/2
COMPARATOR
GND(AIN-)
AIN2
AIN1(AIN+)
HOLD
*( ) APPLIES TO MAX1088/1089
Figure 4. Equivalent Input Circuit
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