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參數(shù)資料
| 型號(hào)： | MAX104CHC |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 【5V, 1Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier |
| 中文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PBGA192 |
| 封裝： | 25 X 25 MM, ESBGA-192 |
| 文件頁(yè)數(shù)： | 6/32頁(yè) |
| 文件大?。?/td> | 637K |
| 代理商： | MAX104CHC |
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M
±5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Trac k/Hold Amplifier
6
_______________________________________________________________________________________
Typic al Operating Charac teristic s
(V
CC
A = V
CC
I = V
CC
D = +5V, V
EE
= -5V, V
CC
O = +3.3V, REFIN connected to REFOUT, f
S
= 1Gsps, T
A
= +25°C, unless otherwise
noted.)
8.00
6.50
10
100
1000
EFFECTIVE NUMBER OF BITS vs.
ANALOG INPUT FREQUENCY
(SINGLE-ENDED ANALOG INPUT DRIVE)
6.75
7.00
7.25
7.50
7.75
M
ANALOG INPUT FREQUENCY (MHz)
E
-12dBFS
-6dBFS
-1dBFS
1250
8.00
6.50
10
100
1000
EFFECTIVE NUMBER OF BITS vs.
ANALOG INPUT FREQUENCY
(DIFFERENTIAL ANALOG INPUT DRIVE)
6.75
7.00
7.25
7.50
7.75
M
ANALOG INPUT FREQUENCY (MHz)
E
-12dBFS
-6dBFS
-1dBFS
1250
49
43
10
100
1000
SIGNAL-TO-NOISE PLUS DISTORTION vs.
ANALOG INPUT FREQUENCY
(DIFFERENTIAL ANALOG INPUT DRIVE)
44
45
46
48
47
M
ANALOG INPUT FREQUENCY (MHz)
S
-12dBFS
-6dBFS
-1dBFS
1250
49
43
10
100
1000
SIGNAL-TO-NOISE PLUS DISTORTION vs.
ANALOG INPUT FREQUENCY
(SINGLE-ENDED ANALOG INPUT DRIVE)
44
45
46
47
48
M
ANALOG INPUT FREQUENCY (MHz)
S
-12dBFS
-6dBFS
-1dBFS
1250
50
30
10
100
1000
SIGNAL-TO-NOISE RATIOvs.
ANALOG INPUT FREQUENCY
(SINGLE-ENDED ANALOG INPUT DRIVE)
34
38
46
42
M
ANALOG INPUT FREQUENCY (MHz)
S
-12dBFS
-6dBFS
-1dBFS
1250
50
30
10
100
1000 1250
SIGNAL-TO-NOISE RATIOvs.
ANALOG INPUT FREQUENCY
(DIFFERENTIAL ANALOG INPUT DRIVE)
34
38
46
42
M
ANALOG INPUT FREQUENCY (MHz)
S
-12dBFS
-6dBFS
-1dBFS
Note 11:
Effective Number of Bits (ENOB) and Signal-to-Noise Plus Distortion (SINAD) are computed from a curve fit referenced to
the theoretical full-scale range.
Note 12:
Total Harmonic Distortion (THD) is computed from the first five harmonics.
Note 13:
Guaranteed by design with a reset pulse one clock period long or greater.
Note 14:
The DREADY to DATA propagation delay is measured from the 50% point on the rising edge of the DREADY signal (when
the output data changes) to the 50% point on a data output bit. This places the falling edge of the DREADY signal in the
middle of the data output valid window, within the differences between the DREADY and DATA rise and fall times, which
gives maximum setup and hold time for latching external data latches.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX104CHC-D | 制造商:Maxim Integrated Products 功能描述:ADC SGL FLASH 1GSPS 8BIT PARALLEL 192PIN ESBGA - Trays |
| MAX104CHC-TD | 制造商:Maxim Integrated Products 功能描述:ADC SGL FLASH 1GSPS 8BIT PARALLEL 192PIN ESBGA - Tape and Reel |
| MAX104EVKIT | 制造商:Maxim Integrated Products 功能描述:KIT PKG - Bulk |
| MAX105 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier |
| MAX1057 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports |
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