參數(shù)資料
型號(hào)： MAX104CHC
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： ADC
英文描述： 【5V, 1Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier
中文描述： 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PBGA192
封裝： 25 X 25 MM, ESBGA-192
文件頁(yè)數(shù)： 27/32頁(yè)
文件大?。?/td> 637K
代理商： MAX104CHC
Bit Error Rates (BER)
Errors resulting from metastable states may occur when
the analog input voltage (at the time the sample is taken)
falls close to the decision point of any one of the input
comparators. Here, the magnitude of the error depends
on the location of the comparator in the comparator net-
work. If it is the comparator for the MSB, the error will
reach full scale. The MAX104’s unique encoding scheme
solves this problem by limiting the magnitude of these
errors to 1LSB; it reduces the probability of these errors
occurring to typically one in every 10
16
clock cycles.
Dynamic Parameter Definitions
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N bits):
SNR
(MAX)
= (6.02
·
N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is calculated by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Effective Number of Bits (ENOB)
ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB
is calculated from a curve fit referenced to the theoreti-
cal full-scale range.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is calculated from the effective number of bits
(ENOB) as follows:
SINAD = (6.02
·
ENOB) + 1.76
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first five harmon-
ics of the input signal to the fundamental itself. This is
expressed as:
where V
1
is the fundamental amplitude, and V
2
through
V
5
are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio, expressed in decibels, of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest spurious
component, excluding DC offset.
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio, expressed in decibels, of
either input tone to the worst 3rd-order (or higher) inter-
modulation products. The input tone levels are at -7dB
full scale.
THD
20 log
V
V
V
V
/ V
22
32
42
52
1
=
+
+
+
M
±5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Trac k/Hold Amplifier
______________________________________________________________________________________
27
Chip Information
TRANSISTOR COUNT: 20,486
SUBSTRATE CONNECTED TO V
EE
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