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參數(shù)資料
| 型號： | MAX1035EUP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT SER 115KSPS 20TSSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 115k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 879mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；4 個單端，雙極；2 個差分，單極；2 個差分，雙極 |
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MAX1034/MAX1035
The MAX1034 has eight single-ended analog input
channels or four differential channels (see the
Block
Diagram at the end of the data sheet). The MAX1035
has four single-ended analog input channels or two dif-
ferential channels. Each analog input channel is inde-
pendently
software
programmable
for
seven
single-ended
input
ranges
(0
to
+VREF/2,
-VREF/2 to 0, 0 to +VREF, -VREF to 0, ±VREF/4, ±VREF/2,
and ±VREF) and three differential input ranges (±VREF/2,
±VREF, and ±2 x VREF). Additionally, all analog input
channels are fault tolerant to ±6V. A fault condition on
an idle channel does not affect the conversion result of
other channels.
Power Supplies
To maintain a low-noise environment, the MAX1034 and
MAX1035 provide separate power supplies for each
section of circuitry. Table 1 shows the four separate
power supplies. Achieve optimal performance using
separate AVDD1, AVDD2, DVDD, and DVDDO supplies.
Alternatively, connect AVDD1, AVDD2, and DVDD
together as close to the device as possible for a conve-
nient power connection. Connect AGND1, AGND2,
AGND3, DGND, and DGNDO together as close to the
device as possible. Bypass each supply to the corre-
sponding ground using a 0.1F capacitor (Table 1). If
significant low-frequency noise is present, add a 10F
capacitor in parallel with the 0.1F bypass capacitor.
Converter Operation
The MAX1034/MAX1035 ADCs feature a fully differen-
tial, successive-approximation register (SAR) conver-
sion technique and an on-chip T/H block to convert
voltage signals into a 14-bit digital result. Both single-
ended and differential configurations are supported
with programmable unipolar and bipolar signal ranges.
Track-and-Hold Circuitry
The MAX1034/MAX1035 feature a switched-capacitor
T/H architecture that allows the analog input signal to be
stored as charge on sampling capacitors. See Figures 2,
3, and 4 for T/H timing and the sampling instants for
each operating mode. The MAX1034/MAX1035 analog
input circuitry buffers the input signal from the sampling
capacitors, resulting in a constant analog input current
with varying input voltage (Figure 5).
8-/4-Channel, ±VREF Multirange Inputs,
Serial 14-Bit ADCs
14
______________________________________________________________________________________
Table 1. MAX1034/MAX1035 Power Supplies and Bypassing
POWER
SUPPLY/GROUND
SUPPLY VOLTAGE
RANGE (V)
TYPICAL SUPPLY
CURRENT (mA)
CIRCUIT SECTION
BYPASSING
DVDDO/DGNDO
2.7 to 5.25
0.2
Digital I/O
0.1F to DGNDO
AVDD2/AGND2
4.75 to 5.25
17.5
Analog Circuitry
0.1F to AGND2
AVDD1/AGND1
4.75 to 5.25
3.0
Analog Circuitry
0.1F to AGND1
DVDD/DGND
4.75 to 5.25
0.9
Digital Control Logic and
Memory
0.1F to DGND
Table 2. Analog Input Configuration Byte
BIT
NUMBER
NAME
DESCRIPTION
7
START
Start Bit. The first logic 1 after
CS goes low defines the beginning of the analog input configuration byte.
6C2
5C1
4C0
Channel-Select Bits. SEL[2:0] select the analog input channel to be configured (Tables 4 and 5).
3
DIF/
SGL
Differential or Single-Ended Configuration Bit. DIF/
SGL = 0 configures the selected analog input channel
for single-ended operation. DIF/
SGL = 1 configures the channel for differential operation. In single-ended
mode, input voltages are measured between the selected input channel and AGND1, as shown in
Table 4. In differential mode, the input voltages are measured between two input channels, as shown in
Table 5. Be aware that changing DIF/
SGL adjusts the FSR, as shown in Table 6.
2R2
1R1
0R0
Input-Range-Select Bits. R[2:0] select the input voltage range, as shown in Table 6 and Figure 7.
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