8-/4-Channel, ±VREF Multirange Inputs, Serial 14-Bit ADCs ______" />
參數(shù)資料
型號: MAX1035EUP+T
廠商: Maxim Integrated Products
文件頁數(shù): 27/31頁
文件大?。?/td> 0K
描述: IC ADC 14BIT SER 115KSPS 20TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 14
采樣率(每秒): 115k
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 879mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個單端,單極;4 個單端,雙極;2 個差分,單極;2 個差分,雙極
MAX1034/MAX1035
8-/4-Channel, ±VREF Multirange Inputs,
Serial 14-Bit ADCs
_______________________________________________________________________________________
5
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Preamplifier Supply Voltage
VAVDD2
4.75
5.25
V
Digital I/O Supply Voltage
VDVDDO
2.70
5.25
V
Internal reference
3
3.5
AVDD1 Supply Current
IAVDD1
External clock mode,
external acquisition
mode, or internal
clock mode
External reference
2.5
3
mA
DVDD Supply Current
IDVDD
External clock mode, external acquisition
mode, or internal clock mode
0.9
2
mA
AVDD2 Supply Current
IAVDD2
External clock mode, external acquisition
mode, or internal clock mode
12
20
mA
DVDDO Supply Current
IDVDDO
External clock mode, external acquisition
mode, or internal clock mode
0.2
1
mA
Partial power-down mode
1.3
mA
Total Supply Current
Full power-down mode
2
A
Power-Supply Rejection Ratio
PSRR
All analog input ranges
±0.125
LSB
TIMING CHARACTERISTICS (Figures 15 and 16)
External clock mode
0.272
62
External acquisition mode
0.288
62
SCLK Period
tCP
Internal clock mode
0.1
s
External clock mode
109
External acquisition mode
92
SCLK High Pulse Width (Note 6)
tCH
Internal clock mode
40
ns
External clock mode
109
External acquisition mode
92
SCLK Low Pulse Width (Note 6)
tCL
Internal clock mode
40
ns
DIN to SCLK Setup
tDS
40
ns
DIN to SCLK Hold
tDH
0ns
SCLK Fall to DOUT Valid
tDO
40
ns
CS Fall to DOUT Enable
tDV
40
ns
CS Rise to DOUT Disable
tTR
40
ns
CS Fall to SCLK Rise Setup
tCSS
40
ns
CS High Minimum Pulse Width
tCSPW
40
ns
SCLK Fall to CS Rise Hold
tCSH
0ns
SSTRB Rise to CS Fall Setup
(Note 4)
40
ns
DOUT Rise/Fall Time
CL = 50pF
10
ns
SSTRB Rise/Fall Time
CL = 50pF
10
ns
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty cycle),
external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (±VREF),
CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
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