參數(shù)資料
型號: MAT02
廠商: Analog Devices, Inc.
英文描述: Low Noise, Matched Dual Monolithic Transistor
中文描述: 低噪音,符合雙單片晶體管
文件頁數(shù): 7/12頁
文件大?。?/td> 264K
代理商: MAT02
MAT02
–7–
REV. C
Figure 18. Log Conformance Test Circuit
LOG CONFORMANCE T E ST ING
T he log conformance of the MAT 02 is tested using the circuit
shown above. T he circuit employs a dual transdiode logarith-
mic converter operating at a fixed ratio of collector currents
that are swept over a 10:1 range. T he output of each transdiode
converter is the V
BE
of the transistor plus an error term which
is the product of the collector current and r
BE
, the bulk emitter
resistance. T he difference of the V
BE
is amplified at a gain of
×
100 by the AMP01 instrumentation amplifier. T he differen-
tial emitter-base voltage (
V
BE
) consists of a temperature-
dependent dc level plus an ac error voltage which is the devia-
tion from true log conformity as the collector currents vary.
T he output of the transdiode logarithmic converter comes
from the idealized intrinsic transistor equation (for silicon):
V
BE
=
kT
qInI
C
S
where
(1)
k
= Boltzmann’s Constant (1.38062
×
10
-23
J/
°
K )
q
= Unit Electron Charge (1.60219
×
10
-19
°
C)
T
= Absolute T emperature,
°
K (=
°
C + 273.2)
I
S
= Extrapolated Current for V
BE
→0
I
C
= Collector Current
An error term must be added to this equation to allow for the
bulk resistance (r
BE
) of the transistor. Error due to the op amp
input current is limited by use of the OP15 BiFET -input op
amp. T he resulting AMP01 input is:
V
BE
=
kT
qInI
C
1
C
2
+ I
C1
r
BE1
– I
C2
r
BE2
(2)
A ramp function which sweeps from 1 V to 10 V is converted by
the op amps to a collector current ramp through each transistor.
Because I
C1
is made equal to 10 I
C2
, and assuming T
A
= 25
°
C,
the previous equation becomes:
V
BE
= 59 mV + 0.9 I
C1
r
BE
(
r
BE
~ 0)
As viewed on an oscilloscope, the change in
V
BE
for a 10:1
change in I
C
is then displayed as shown below:
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