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參數(shù)資料
| 型號(hào)： | MACH210A-10JC |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | High-Density EE CMOS Programmable Logic |
| 中文描述： | EE PLD, 10 ns, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 6/47頁(yè) |
| 文件大?。?/td> | 347K |
| 代理商： | MACH210A-10JC |
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MACH210A-10/12 (Com’l)
14
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Unit
CIN
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25
°C,
6
pF
COUT
Output Capacitance
VOUT = 2.0 V
f = 1 MHz
8
pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
Min
Max
Min
Max
Unit
tPD
Input, I/O, or Feedback to Combinatorial Output
(Note 3)
10
12
ns
D-Type
6.5
7
ns
T-Type
7.5
8
ns
tH
Register Data Hold Time
0
ns
tCO
Clock to Output (Note 3)
6
8
ns
tWL
Clock
LOW
5
6
ns
tWH
Width
HIGH
5
6
ns
D-Type
80
66.7
MHz
T-Type
74
62.5
MHz
fMAX
D-Type
100
83.3
MHz
T-Type
91
76.9
MHz
100
83.3
MHz
tSL
Setup Time from Input, I/O, or Feedback to Gate
6.5
7
ns
tHL
Latch Data Hold Time
0
ns
tGO
Gate to Output (Note 3)
7
10
ns
tGWL
Gate Width LOW
5
6
ns
tPDL
Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch
12
14
ns
tSIR
Input Register Setup Time
2
ns
tHIR
Input Register Hold Time
2
ns
tICO
Input Register Clock to Combinatorial Output
13
15
ns
tICS
Input Register Clock to Output Register Setup
D-Type
10
12
ns
T-Type
11
13
ns
tWICL
Input Register
LOW
5
6
ns
tWICH
Clock Width
HIGH
5
6
ns
fMAXIR
Maximum Input Register Frequency
1/(tWICL + tWICH)
100
83.3
MHz
tSIL
Input Latch Setup Time
2
ns
tHIL
Input Latch Hold Time
2
ns
tIGO
Input Latch Gate to Combinatorial Output
14
17
ns
tIGOL
Input Latch Gate to Output Through Transparent
Output Latch
16
19
ns
tSLL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
8.5
9
ns
tIGS
Input Latch Gate to Output Latch Setup
11
13
ns
Maximum
Frequency
(Note 1)
Setup Time from Input, I/O,
or Feedback to Clock
External Feedback
1/(tS + tCO)
Internal Feedback (fCNT)
No Feedback
1/(tS + tH)
-10
-12
tS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MACH210A-10VC | High-Density EE CMOS Programmable Logic |
| MACH210A-12JC | High-Density EE CMOS Programmable Logic |
| MACH210A-12VC | High-Density EE CMOS Programmable Logic |
| MACH210A-7 | High-Density EE CMOS Programmable Logic |
| MACH215-12JC | High-Density EE CMOS Programmable Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MACH210A-10VC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MACH210A-12 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic |
| MACH210A-12JC | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density EE CMOS Programmable Logic |
| MACH210A-12JI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic |
| MACH210A-12VC | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density EE CMOS Programmable Logic |
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