參數(shù)資料
型號(hào)： MACH111SP-7VC
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： High-Performance EE CMOS Programmable Logic
中文描述： EE PLD, 7.5 ns, PQFP44
封裝： TQFP-44
文件頁(yè)數(shù)： 47/48頁(yè)
文件大?。?/td> 1136K
代理商： MACH111SP-7VC
8
MACH 1 & 2 Families
The output macrocell (Figure 3) sends its output back to the switch matrix, via internal feedback,
and to the I/O cell. The feedback is always available regardless of the conguration of the I/O cell.
This allows for buried combinatorial or registered functions, freeing up the I/O pins for use as
inputs if not needed as outputs. The basic output macrocell congurations are shown in Figure 4.
The buried macrocell (Figure 5) does not send its output to an I/O cell. The output of a buried
macrocell is provided only as an internal feedback signal which feeds the switch matrix. This
allows the designer to generate additional logic without requiring additional pins. The buried
macrocell can also be used to register or latch inputs. The input register is a D-type ip-op; the
input latch is a transparent-low D-type latch. Once congured as a registered or latched input, the
buried macrocell cannot generate logic from the product-term array. The basic buried macrocell
congurations are shown in Figure 6.
Figure 3. Output Macrocell
Note:
1. Latch option available on MACH 2 devices only.
CLK0
CLKn
1
0
1
0
AR
AP
Q
D/T/L1
To
Switch
Matrix
Sum of Products
from Logic
Allocator
PAL-Block
Asynchronous
Preset
To I/O
Cell
PAL-Block
Asynchronous
Reset
14051K-004
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