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參數(shù)資料
| 型號： | MAC7141 |
| 廠商： | Motorola, Inc. |
| 英文描述： | MAC7100 Microcontroller Family Hardware Specifications |
| 中文描述： | MAC7100微控制器系列硬件規(guī)格 |
| 文件頁數(shù)： | 20/48頁 |
| 文件大?。?/td> | 1514K |
| 代理商： | MAC7141 |
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20
MAC7100 Microcontroller Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Electrical Characteristics
3.9.1
Read and Write Bus Cycles
Table 23 lists processor bus output timings. Read/write bus timings listed in Table 23 are shown in Figure 7
and Figure 8.
Table 23. External Bus Output Timing Specifications
Num
C
Rating
Symbol
Min
Max
Unit
Control Outputs
L6a
CLKOUT high to chip selects valid
1
CLKOUT high to byte select (BS[1:0]) valid
2
1
2
3
CS
n
transitions after the falling edge of CLKOUT.
BS
n
transitions after the falling edge of CLKOUT.
OE transitions after the falling edge of CLKOUT.
t
CHCV
t
CHBV
—
0.5t
CYC
+ 10
0.5t
CYC
+ 10
ns
L6b
—
ns
L6c
CLKOUT high to output select (OE) valid
3
t
CHOV
—
0.5t
CYC
+ 10
ns
L7a
CLKOUT high to control output (BS[1:0], OE) invalid
t
CHCOI
t
CHCI
0.5t
CYC
+ 2
0.5t
CYC
+ 2
—
ns
L7b
CLKOUT high to chip selects invalid
—
ns
Address and Attribute Outputs
L8
CLKOUT high to address (ADDR[21:0]) and control
(R/W) valid
t
CHAV
—
10
ns
L9
CLKOUT high to address (ADDR[21:0]) and control
(R/W) invalid
t
CHAI
2
—
ns
Data Outputs
L10
CLKOUT high to data output (DATA[15:0]) valid
t
CHDOV
t
CHDOI
t
CHDOZ
—
13
ns
L11
CLKOUT high to data output (DATA[15:0]) invalid
2
—
ns
L12
CLKOUT high to data output (DATA[15:0]) high impedance
—
9
ns
F
Freescale Semiconductor, Inc.
n
.
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