參數(shù)資料
型號: MAC7116VAG50R2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-144
文件頁數(shù): 41/56頁
文件大?。?/td> 1216K
代理商: MAC7116VAG50R2
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Device Pin Assignments
Freescale Semiconductor
46
4.6
MAC7111 / MAC7116 Pin Diagram
Figure 20. Pin Assignments for MAC7111 / MAC7116 in 144-pin LQFP
MAC7111 / MAC7116
PF6
PF5
PF4
PF3
PF2
PF1
PF0
PC8
PC9
PC10
PC11
PG1
2
PG1
3
PA
1
5
PA
1
4
PA
1
3
PD11
PD12
PD0
PD1
PB9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PE9
PE8
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PA7
PA8
PA9
PA10
PA11
PA12
PD5
PC15
PC14
PC13
PC12
VDDX
VSSX
PD15
PD14
PD13
PD4
PD3
TA / AS
PB15
PB14
PB13
PB12
PB11
PB10
PG4
PG5
PG8
PG9
PG10
PG11
PG6
PG7
PC0
PC1
PC2
PC3
VSSX
VDDX
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PF15
PF14
PF13
PF12
PC4
PC5
PC6
PC7
PF11
PF10
PF9
PF8
PF7
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
RE
SET
V
SS
X
V
DD
X
V
DD
2.
5
V
SS
2.
5
V
SS
R
V
DD
R
V
DD
PL
L
XFC
V
SS
PL
L
EX
T
A
L
XT
AL
TEST
V
SS
X
V
DD
X
144 LQFP
/T
X
D_
A
/RXD_A
/T
X
D_
B
/RXD_B
/T
X
D_
C
/RXD_C
/D
A
T
A
0
/D
A
T
A
1
/D
A
T
A
2
/D
A
T
A
3
/D
A
T
A
4
/D
A
T
A
5
/D
A
T
A
6
TMS
TCK
TDO
TDI
V
DD
2.
5
V
SS
2.
5
V
SS
X
V
DD
X
/ADDR21
/ADDR20
/ADDR19
/ADDR18
/ADDR17
/AN15_
A
/AN14_
A
/AN13_
A
/AN12_
A
/AN11_
A
/AN10_
A
V
SS
A
VRL
VRH
V
DD
A
CNTX_A
CNRX_A
CNTX_C
CNRX_C
CNTX_D
CNRX_D
CNTX_B
CNRX_B
ADDR0
ADDR1
ADDR2
ADDR3
SDA
SCL
SIN_A
SOUT_A
SCK_A
PCS0_A
PCS1_A
PCS2_A
PCS5_A
eMIOS15
eMIOS14
eMIOS13
eMIOS12
ADDR4
ADDR5
ADDR6
ADDR7
eMIOS11
eMIOS10
eMIOS9
eMIOS8
eMIOS7
SS_A
PCSS_A
/
eM
IO
S
6
eM
IO
S
5
eM
IO
S
4
eM
IO
S
3
eM
IO
S
2
eM
IO
S
1
eM
IO
S
0
AD
D
R
8
AD
D
R
9
AD
D
R
10
AD
D
R
11
RX
D
_
D
TXD_
D
DA
T
A
1
5
DA
T
A
1
4
DA
T
A
1
3
OE
CS
2
BS
0
BS
1
P
C
S0_B
NEX
P
R
NEX
P
S
MODB
MOD
A
SS
_B
/
/ AN9_A
/ AN8_A
/ AN7_A
/ AN6_A
/ AN5_A
/ AN4_A
/ AN3_A
/ AN2_A
/ AN1_A
/ AN0_A
/ DATA7
/ DATA8
/ DATA9
/ DATA10
/ DATA11
/ DATA12
/ ADDR16
/ ADDR15
/ ADDR14
/ ADDR13
/ ADDR12
/ R/W
/ CS0
/ CS1
/ IRQ
/ XIRQ
/ CLKOUT
/ SIN_B
/ SOUT_B
/ SCK_B
/ PCS1_B
/ PCS2_B
/ PCS5_B
/ RDY'
/ MSEO'
/ MDO1'
/ MDO0'
/ EVTI'
/ EVTO'
/ MCKO'
/ XCLKS
/ PCSS_B
PG
3
PG
2
PG
1
PG
0
PG
15
PG
14
PA
0
PA
1
PA
2
PA
3
PA
4
PA
5
PA
6
PD1
0
PD9
PD8
PD7
PD6
PE
15
PE
14
PE
13
PE
12
PE
11
PE
10
/M
C
K
O
/EV
TO
/EV
TI
/M
D
O0
/M
D
O1
/M
S
E
O
/RDY
1. PD2 function not available on L49P mask set devices.
PD2(1)
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