參數(shù)資料
型號： MAC7116VAG50R2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-144
文件頁數(shù)： 11/56頁
文件大?。?/td> 1216K
代理商： MAC7116VAG50R2
ElectricalCharacteristics
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
19
3.8.6
Startup
Table 23 summarizes several startup characteristics. Refer to Section 4.3.6.10, “CRG Operating Mode
Details,” in the MAC7100 Microcontroller Family Reference Manual (MAC7100RM) for details.
3.8.6.1
Power On and Low Voltage Reset (POR and LVR)
The VPORR and VPORA levels are derived from VDD2.5. The VLVRA level is derived from VDD2.5. They
are also valid if the device is powered externally. After releasing a POR or LVR reset, the oscillator and
clock quality checks start. After tCQOUT (Table 19, J4) if no valid oscillation is detected, the MCU will
start using the internal self-generated clock. The minimum startup time is given by tuposc (Table 19, J3).
3.8.6.2
SRAM Data Retention
SRAM content integrity is guaranteed if the CRGFLG[PORF] bit is not set following a reset operation.
3.8.6.3
External Reset
When external reset is asserted for a time greater than PWRSTL, the CRG generates an internal reset and
the CPU fetches the reset vector without a clock quality check, if there was stable oscillation before reset.
3.8.6.4
Stop Recovery
The MCU can return from stop to run mode in response to an external interrupt or an API. Two delays
occur before the MCU resumes execution. First, the voltage regulator must exit reduced power mode and
return to full performance mode (this assumes that the internal regulator is used rather than driving VDD2.5
and VDDPLL with an external regulator). Second, a clock quality check is performed in the same manner
as for a power-on reset before releasing the clocks to the system.
3.8.6.5
Pseudo Stop Recovery
Recovery from pseudo stop mode is similar to stop mode in that the VREG must return to FPM, but since
the oscillator is not stopped there is no delay for clock stabilization. The MCU is returned to run mode by
internal or external interrupts.
3.8.6.6
Doze Recovery
Recovery from doze mode avoids both the VREG and oscillator recovery periods. The MCU is returned
to run mode by internal or external interrupts.
Table 23. CRG Startup Characteristics
Num C
Rating
Symbol
Min
Typ
Max
Unit
L1
D Reset input pulse width
PWRSTL
2—
—
tOSC
L2
D Startup from Reset
nRST
192
—
196
tOSC
L3
D XIRQ, IRQ pulse width, edge-sensitive mode
PWIRQ
20
—
ns
相關(guān)PDF資料
PDF描述
MAC7121VAG40 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP112
MAX9380ESA+ 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO8
MB2052BB-T MB SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PQFP52
MB2541BB,518 MB SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PQFP52
MB2646BB-T MB SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PQFP52
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAC7116VFU50 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller Family Hardware Specifications
MAC7116VPV50 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller Family Hardware Specifications
MAC7116VVF50 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller Family Hardware Specifications
MAC7116VVM50 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller Family Hardware Specifications
MAC7121 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller Family Reference Manual
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*