參數(shù)資料
型號: MA838
廠商: Zarlink Semiconductor Inc.
英文描述: SINGLE PHASE PULSE WIDTH MODULATION WAVEFORM GENERATOR
中文描述: 單相脈寬調(diào)制波形發(fā)生器
文件頁數(shù): 6/13頁
文件大?。?/td> 314K
代理商: MA838
5
MA838
Fig. 4 Intel bus timing definitions
Fig. 5 Motorola bus timing definitions
Parameter
ALE high period
Delay time, ALE to WR
WR low period
Delay time, WR high to ALE high
CS setup time
CS hold time
Address setup time
Address hold time
Data setup time
Data hold time
Symbol
t
1
t
2
t
3
t
4
t
8
t
9
t
10
t
15
t
11
t
12
Min.
70
40
200
40
20
0
30
30
100
25
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 1 Intel bus timings at V
DD
= 5V, T
AMB
= 25°C
Parameter
AS high period
Delay time, as low to DS high
DS high period
Delay time, DS low to AS high
DS low period
DS high to R/W low setup time
R/W hold time
CS setup time
CS hold time
Address setup time
Address hold time
Write data setup time
Write data hold time
Min.
90
40
210
40
200
10
10
20
0
30
30
110
30
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 2 Motorola bus timings at V
DD
= 5V, T
AMB
= 25°C
Symbol
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
15
t
11
t
12
CONTROLLING THE MA838
The MA838 is controlled by loading data into two 24-bit
registers via the microprocessor interface. These registers
are the initialisation register and the control register.
The initialisation register would normally be loaded prior to
the PWM outputs being activated and sets up the basic
operating parameters associated with the load and inverter.
This data would not normally be updated during PWM
operation.
The control register is used to control the PWM outputs
(and hence the load) during operation e.g., stop/start, speed
etc. and would normally be loaded and changed only after the
initialisation register has been loaded.
As the MOTEL bus interface is restricted to an 8-bit wide
format, data to be loaded into either of the 24-bit register is
first written to three 8-bit temporary registers R0, R1 and R2
before being transferred to the desired 24-bit register. The
data is accepted (and acted upon) only when transferred to
one of the 24-bit registers.
Transfer of data from the temporary registers to either the
initialisation register or the control register is achieved by a
write instruction to a dummy register. Writing to dummy register R3
results in data transfer from R0, R1 and R2 to the control register,
while writing to dummy register R4 transfers data from R0, R1
and R2 to the initialisation register. It does not matter what data
is written to the dummy registers R3 and R4 as they are not real
registers. It is merely the write instruction to either of these
registers which is acted upon in order to load the initialisation and
control registers.
Register
R0
R1
R2
R3
R4
Comment
Temporary register R0
Temporary register R1
Temporary register R2
Transfers control data
Transfers initialisation data
AD
1
0
0
1
1
0
AD
2
0
0
0
0
1
AD
0
0
1
0
1
0
Table 3 MA838 register addressing
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