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參數(shù)資料
| 型號： | M926-02I600.0000LF |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 600 MHz, OTHER CLOCK GENERATOR, CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 321K |
| 代理商： | M926-02I600.0000LF |
M926-02 Datasheet Rev 0.7
3 of 8
Revised 30Jul2004
Integr ated Circuit Systems , Inc. ● Ne tw o r ki ng & C o mmun ica t io ns ● ww w. icst.com ● tel (508 ) 85 2-54 00
M926-02
VCSO BASED CLOCK GENERATOR
Preliminar y In f o r m atio n
FUNCTIONAL DESCRIPTION
The M926-02 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks
synchronized to an input reference clock.
The M926-02 combines the flexibility of a VCSO
(Voltage Controlled SAW Oscillator) with the stability of
a crystal oscillator.
Input Reference
The 19.44MHz input reference can either be an external,
discrete crystal device or a stable external clock source
such as a packaged crystal oscillator:
If an external crystal is used with the on-chip crystal
oscillator circuit (XTAL OSC), the external crystal
should be a parallel-resonant, fundamental mode
crystal. Apply it to the XTAL_1 / REF_IN and XTAL_2 input
pins. External crystal load capacitors are also
required.
If an external LVCMOS/LVTTL clock source is used,
apply it to the XTAL_1 / REF_IN input pin.
In either case, the reference clock is supplied directly to
the phase detector of the PLL.
The EX_CLK pin is available for a clock feed-through
mode for testing. See “External Clock Feed-through”
on pg. 3.
The PLL
The PLL (Phase Locked Loop) includes the phase
detector, the VCSO, and a feedback divider (labeled
“M Divider”).
The feedback divider is a digital circuit that divides the
VCSO output frequency by a numerical value “M” in
order to match the input reference frequency.
By controlling the frequency and phase of the VCSO,
the phase detector precisely locks the frequency and
phase of the feedback divider output to that of the input
reference. This creates an output frequency that is a
multiple of the reference frequency (which is output
from the VCSO).
The relationship between the VCSO output frequency,
the M Divider, and the input reference frequency is
defined as follows:
For the M926-02-622.0800 (see “Ordering Information” on pg. 8):
VCSO output frequency = 622.08MHz
M = 32
Input reference frequency = 19.44MHz
Therefore, for the M926-02-622.0800:
622.08
MHz = 32
19.44
MHz
The VCSO center output frequency of 622.08MHz
enables the product of
to fall within the lock range of the VCSO.
Post-PLL Divider
The M926-02 also features a post-PLL divider (labeled
“P Divider”) for selecting one of two output frequencies
(e.g., 622.08 or 155.52 MHz).
The FOUT_SEL pin determines the P Divider value:
When FOUT_SEL = 0, P = 1.
When FOUT_SEL = 1, P = 4.
External Clock Feed-through
The EXT_CLK pin provides an input for an external
single-ended clock that directly drives the LVPECL
clock outputs. This pin is intended for system debugging
and performance evaluation..
STOP Clock
The STOP pin puts the output clock into a static condition.
Fvcso
M
Fxtal
×
=
EN_EXT_CLK
Logic 1 enables the EXT_CLK input.
Use Logic 0 for normal operation.
EXT_CLK
Apply an external LVCMOS/LVTTL clock source
for 0 to 200 MHz feed-through operation.
Leave inactive for normal operation.1
Note 1: In applications where EXT_CLK is active while the SAW PLL
signal path is enabled, it is necessary to gate the EXT_CLK to
minimize jitter in the LVPECL output pairs. See the PCB Design
Guidelines for ICS SAW PLLs application note at
Logic 1 Output clocks are static
Logic 0 Output clocks enabled for normal operation
×
M
input crystal frequency
×
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M926-02-622.0800LF | 622.08 MHz, OTHER CLOCK GENERATOR, CQCC36 |
| M926-02-622.0800LF | 622.08 MHz, OTHER CLOCK GENERATOR, CQCC36 |
| M926-02I622.0800LF | 622.08 MHz, OTHER CLOCK GENERATOR, CQCC36 |
| M926-02-622.0800 | 622.08 MHz, OTHER CLOCK GENERATOR, CQCC36 |
| M926-02-600.0000 | 600 MHz, OTHER CLOCK GENERATOR, CQCC36 |
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