M926-02 Datasheet Rev 0.7
Revised 30Jul2004
M926-02
VCSO BASED CLOCK GENERATOR
Prelimina r y Inf o r m ation
GENERAL DESCRIPTION
The M926-02 is a PLL (Phase Locked Loop) based
clock generator that uses an
internal VCSO (Voltage Controlled
SAW Oscillator) to produce a very
low jitter output clock. From the
M926-02-622.0800
, an output clock
frequency of 622.08 or 155.52MHz
is provided from six LVPECL clock
output pairs. (Other frequencies
are available; consult factory.) The accuracy of the
output frequency is assured by the internal PLL that
phase-locks the internal VCSO to the reference input
frequency (19.44MHz for the M926-02-622.0800). The input
reference can either be an external crystal, utilizing the
internal crystal oscillator, or a stable external clock
source such as a packaged crystal oscillator.
FEATURES
◆ Output clock frequency range 150MHz to 700MHz
(Consult factory for frequency availability)
◆ Selectable divider chooses one of two frequencies
◆ Six identical LVPECL output pairs (same frequency)
◆ Jitter 0.7ps rms (@622.08MHz, over 12kHz-20MHz), typ.
◆ Ideal for OC-48/STM-16 clock reference
◆ Output-to-output skew < 100ps
◆ External XTAL or LVCMOS reference input
◆ Selectable external feed-through clock input
◆ STOP clock control (Logic 1 stops output clocks)
◆ Integrated SAW (surface acoustic wave) delay line
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
PIN ASSIGNMENT (9 x 9 mm SMT)
Figure 1: Pin Assignment
SIMPLIFIED BLOCK DIAGRAM
Example Output Frequency Configurations
(M926-02-622.0800)
Ref Clock
Frequency
(MHz)
VCSO
Frequency
(MHz)
P Divider
Value
Output
Frequency
(MHz)
19.44
622.08
1
622.08
4155.52
N
nO
M926-02-622.08 (Other Frequencies Available)
Divider
Select
External
Loop Filter
M926-02 VCSO Based Clock Generator