參數(shù)資料
型號: M89341Y-90T1T
廠商: 意法半導體
英文描述: In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems for MCUs
中文描述: 在系統(tǒng)可編程ISP的多內(nèi)存和邏輯FLASHPSD系統(tǒng)的微控制器
文件頁數(shù): 5/7頁
文件大?。?/td> 52K
代理商: M89341Y-90T1T
5/7
M89 FAMILY
erased without the use of the MCU. The primary
Flash memory can also beprogrammed in-system
by
the
MCU
executing
algorithms out of the secondary memory, or
SRAM.
The
secondary
programmed thesame way by executing out of the
primary
Flash
memory. The
FLASH+PSD
Configuration
programmed through the JTAG port or a device
insertion programmer. Table 5 indicates which
programming methods can program different
functional blocks of the FLASH+PSD.
Power Management Unit (PMU)
The Power Management Unit (PMU) gives the
user controlof the power consumptionon selected
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during
MCU inactivity. The APD Unit has a Power-down
mode that helps reduce power consumption.
The FLASH+PSD also has some bits that are
configured at run-time by the MCU to reduce
power consumption of the GPLD. The Turbo bit in
the PMMR0 register can be reset to 0 and the
GPLD latches its outputs and goes to sleep until
the next transition on its inputs.
Additionally, bits in thePMMR2 register can beset
by the MCU to block signals from entering the
GPLD to reduce power consumption. Please see
the full data sheet for details.
the
programming
memory
can
be
PLD
blocks
or
can
other
be
SECURITY AND NVM SECTOR PROTECTION
A security bit in the Protection Register enables
the software project, coded inthe FLASH+PSD, to
be locked up. This bit is only accessible by the
system designerfrom theJTAG serial port, or from
a parallel insertion programmer. It cannot be
accessed from the MCU. The only way a security
bit can be cleared is to erase the entirechip.
The contents of the sectors of the primary and
secondary NVM blocks can beprotected using bits
in the Protection Registers. These bits are
accessible from the MCU in the application code,
or
from
a
programmer
procedure.
during
the
set-up
Table 3. PLD I/O
Name
Inputs
Outputs
Product
Terms
Decode PLD (DPLD)
57
14
39
General PLD (GPLD)
57
19
114
Table 4. JTAG SIgnals on Port C
Port C Pins
JTAG Signal
PC0
TMS
PC1
TCK
PC3
TSTAT
PC4
TERR
PC5
TDI
PC6
TDO
Table 5. Methods of Programming Different Functional Blocks of the FLASH+PSD
Functional Block
JTAG Programming
Device Programmer
IAP
Primary Flash Memory
Yes
Yes
Yes
Secondary EEPROM or Flash memory
Yes
Yes
Yes
PLD Array (DPLD and GPLD)
Yes
Yes
No
FLASH+PSD Configuration
Yes
Yes
No
OTP Row
No
Yes
Yes
相關(guān)PDF資料
PDF描述
M8PSDSOFT M8 FLASHPSD System Development Tools
M902-01-156.2500 VCSO BASED GBE CLOCK GENERATOR
M902-01I125.0000 VCSO BASED GBE CLOCK GENERATOR
M902-01I156.2500 VCSO BASED GBE CLOCK GENERATOR
M902-01I187.5000 VCSO BASED GBE CLOCK GENERATOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M89341Y-90T6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems for MCUs
M89342W-15K1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems for MCUs
M89342W-15K6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems for MCUs
M89342W-15T1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems for MCUs
M89342W-15T6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems for MCUs