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參數(shù)資料
| 型號： | M902-01I156.2500 |
| 英文描述： | VCSO BASED GBE CLOCK GENERATOR |
| 中文描述： | 銀杏葉提取物才能開發(fā)出復雜基于時鐘發(fā)生器 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 328K |
| 代理商： | M902-01I156.2500 |
M902-01 Datasheet Rev 2.1
M902-01 VCSO Based GbE Clock Generator
Revised 24Jun2004
Integrated Circuit Systems, Inc.
●
Networking & Communications
●
www.icst.com
●
tel (508) 852-5400
M902-01
VCSO B
ASED
G
B
E C
LOCK
G
ENERATOR
Integrated
Circuit
Systems, Inc.
P r o d u c t D a t a S h e e t
G
ENERAL
D
ESCRIPTION
The M902-01 is a PLL (Phase Locked Loop) based
clock generator that uses an
internal VCSO (Voltage Controlled
SAW Oscillator) to produce a very
low jitter output clock. It is ideal for
Gigabit Ethernet. The output clock
(frequency of
156.25
or
187.50
MHz
for example) is provided from two
LVPECL clock output pairs. (Specify frequency at time
of order.) The accuracy of the output frequency is
assured by the internal PLL, which phase-locks the
internal VCSO to the reference input frequency (
25
or
30
MHz for example). The input reference can either
be an external crystal, utilizing the internal crystal
oscillator, or a stable external clock source such as
a packaged crystal oscillator.
F
EATURES
◆
Output clock frequency from 125MHz to 190MHz
(Consult factory for frequency availability)
◆
Two identical LVPECL output pairs
◆
Integrated SAW (surface acoustic wave) delay line
◆
Low jitter 0.5ps rms (over 12kHz-20MHz)
◆
Ideal for Gigabit Ethernet
clock reference
◆
Output-to-output skew < 100
ps
◆
External XTAL or LVCMOS reference input
◆
Selectable external feed-through clock input
◆
STOP
clock control (Logic 1 stops output clocks)
◆
Industrial temperature grade available
◆
Single 3.3V power supply
◆
Small 9 x 9 mm SMT (surface mount) package
S
IMPLIFIED
B
LOCK
D
IAGRAM
M902-01
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
Figure 1: Pin Assignment
Figure 2: Simplified Block Diagram
Example Output Frequency Configurations
Ref Clock
Frequency
(MHz)
PLL
Ratio
Output
Frequency
1
(MHz)
Note 1: Specify output clock frequency at time of order
Application
20
25
30
25/4
125.00
156.25
187.50
GbE
10GbE
12GbE
Table 1: Example Output Frequency Configurations
M902-01
(Top V iew)
1
2
3
4
5
6
7
8
9
X
G
S
E
E
N
N
N
V
NC
NC
nFOUT1
FOUT1
GND
nFOUT0
FOUT0
VCC
GND
XTAL_2
NC
NC
NC
NC
VCC
DNC
DNC
DNC
n
O
V
n
n
O
G
G
G
1
2
2
2
2
2
2
2
2
28
29
30
31
32
33
34
35
36
18
17
16
15
14
13
12
11
10
XTAL
OSC
O
1
External
Crystal
or
Reference
Clock Input
(e.g., 25 or 30MHz)
LVPECL
Output
Clock Pairs
(e.g., 156.25
or 187.50MHz)
Divider
External
Clock
Input
External
Clock
Select
Output
Clock STOP
Control
VSCO
Frequency
Multiplying
PLL
External
Loop Filter
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