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參數(shù)資料
| 型號(hào)： | M8803F2W-15T1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁(yè)數(shù)： | 43/85頁(yè) |
| 文件大?。?/td> | 601K |
| 代理商： | M8803F2W-15T1 |
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M88 FAMILY
48/85
Table 32. M88 Family Timing and Stand-by Current during Power Down Mode
Note: 1. Power Down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo Bit.
2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo bit is off.
Mode
PLD Propagation
Delay
Memory
Access Time
Access Recovery Time
to Normal Access
Typical Stand-by Current
5V VCC
3V VCC
Power Down
Normal tPD (Note
1)
No Access
tLVDV
50
A (Note 2)25 A (Note 2)
Figu re 33. APD Logic Block
APD EN
PMMR0 BIT 1=1
ALE
RESET
CSI
CLKIN
TRANSITION
DETECTION
EDGE
DETECT
APD
COUNTER
POWER DOWN
(PDN)
DISABLE BUS
INTERFACE
EEPROM SELECT
FLASH SELECT
SRAM SELECT
PD
CLR
PD
DISABLE
FLASH/EEPROM/SRAM
PLD
SELECT
AI02891
states keeps the PLD out of standby mode, but not
the memories.
t The PSD Chip Select Input (CSI) on all families
can be used to disable the internal memories,
placing them in standby mode even if inputs are
changing. This feature does not block any internal
signals or disable the PLDs. This is a good
alternative to using the APD logic. There is a slight
penalty in memory access time when the CSI
signal makes its initial transition from deselected
to selected.
t The PMMR registers can be written by the MCU
at run-time to manage power. All three families
support “blocking bits” in these registers that are
set to block designated signals from reaching both
PLDs. Current consumption of the PLDs is directly
related to the composite frequency of the changes
on their inputs (see Figure 36 and Figure 37).
Significant power savings can be achieved by
blocking signals that are not used in DPLD or
CPLD logic equations. Unique to the M88x3Fxx
FLASH+PSD devices is the Turbo Bit in the
PMMR0 register. This bit can be set to disable the
Turbo Mode feature (default is Turbo Mode on).
While Turbo Mode is disabled, the PLDs can
achieve standby current when no PLD inputs are
changing (zero DC current). Even when inputs do
change, significant power can be saved at lower
frequencies (AC current), compared to when
Turbo Mode is enabled. When the Turbo Mode is
enabled,
there is
a
significant
DC
current
component and the AC component is higher.
Automatic Power Down (APD) Unit and Power
Down Mode
The APD Unit, shown in Figure 33, puts the PSD
into Power Down Mode by monitoring the activity
of the address strobe (ALE/AS). If the APD unit is
enabled, as soon as activity on the address strobe
stops, a four bit counter starts counting. If the
address strobe remains inactive for fifteen clock
periods of the CLKIN signal, the Power Down
(PDN) signal becomes active, and the PSD will
enter into Power Down Mode, discussed next.
Power Down Mode
By default, if you enable the PSD APD unit, Power
Down Mode is automatically enabled. The device
will enter Power Down Mode if the address strobe
(ALE/AS) remains inactive for fifteen CLKIN (pin
PD1) clock periods.
The following should be kept in mind when the
PSD is in Power Down Mode:
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| M8813F3W-15K1 | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
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相關(guān)代理商/技術(shù)參數(shù) |
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| M8805/100-007 | 制造商:OTTO Engineering Inc 功能描述:M8805/100-007 |
| M8805/100-009 | 制造商:OTTO Engineering Inc 功能描述:M8805/100-009 |
| M8805/100-010 | 制造商:OTTO Engineering Inc 功能描述:M8805/100-010 |
| M8805/100-015 | 制造商:OTTO Engineering Inc 功能描述:M8805/100-015 |
| M8805/100-016 | 制造商:OTTO Engineering Inc 功能描述:M8805/100-016 |
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